Shulou(Shulou.com)11/24 Report--

From design, to production, to testing, adjustment, reproduction, to the final factory and market, a small chip, to go through a complex and long process.

Many semiconductor practitioners can count on these processes. However, very few people can actually enter the world's top-level and top-secret wafer factories and chip testing laboratories equipped with the most cutting-edge technology to witness the birth of a chip at a close distance.

I'm not exaggerating with you: not to mention that customers can't get in, even Intel, which employs 120000 people around the world, has only about 1-2% of its employees in and out of its chip workshop; 99% of its employees don't even get a chance to take a picture with the wafer.

Today, the proud Silicon can finally say that we have not only taken a photo with the Raptor Lake wafer (the upcoming 13th-generation Kouri processor), but also dressed in the "rabbit suit" of the clean workshop:

△ photo source: Silicon via Intel

Ten minutes before this photo was taken, I had just come out of Intel's Israel Fab 28 fab. The world's top semiconductor company, which can be equated with "chip technology innovation", recently opened its long-famous fab for the first time to analysts from more than a dozen countries.

Don't give up that we haven't seen the world: for any technology practitioner, this is a "once-in-a-lifetime" opportunity. Even the top-notch Linus Tech Tips of YouTube technology shouted "I can die now." (note: the die here is a pun, and it means grains. )

There is no reason to have good things alone. Next, make a cup of coffee, open a bag of snacks, and walk with the Silicon Star into the Intel Israel Fab 28 fab and the IDC chip testing lab to find out.

/ enter the factory / Fab 28 is Intel's first non-American fab, completed in 1996 and located in the Israeli town of Kiryat Gat.

The Palestinian-Israeli region is suffering from war, and most people will feel that it is not safe to build a factory here. However, the real situation is: considering the talent reserve, policy advantages, the drip effect of military technology and other factors, Intel came here as early as 1974 to establish the Israeli design center IDC (later renamed as the Israeli R & D center IDC). It is logical to put the factory and the R & D center together.

Intel later established Fab 8 in Jerusalem and then Fab 28 in the town of Gath. To this day, the plant is still the main producer of core processors, which means a lot to Intel.

△ Fab 28 main office building Photo Source: du Chen / Silicon Man

View of the building where the dust-free workshop of △ Fab 28 is located. Source: du Chen / Silicon Man

As mentioned earlier, very few Intel employees have access to the factory production environment, or even dust-free workshops. As soon as I entered the building, I saw a warning sign on the "protected area" (protected area), meaning that the office and working environment in these areas may be highly classified:

View of the building where the dust-free workshop of △ Fab 28 is located. Source: du Chen / Silicon Man

Before entering the dust-free workshop of the Fab 28 fab, we first met Daniel Benatar, the head of Intel's global chip production. He introduced the key processes of chip production that can be seen with his own eyes at Fab 28, including ion implantation (implant), diffusion (diffusion), lithography, etching (etch), thin film, flattening (planarization), controlled folding chip connection (C4), etc.

△ Daniel Benatar explains the changes in transistor circuit design Photo Source: Silicon via Intel

/ the first stop: clean / the tour officially begins. The "tour guide" of my group is Oren Cohen, factory manager of Fab 28.

Under his leadership, we shuttled back and forth in the office building, went upstairs and downstairs several times, and finally reached the entrance to the clean room / dust-free workshop (Cleanroom). There is a security gate where only authorized employees can swipe their cards to enter.

△ Picture Source: Linus Tech Tips

In order to avoid carrying pollutants, everyone must wear protective clothing nicknamed "bunny suit" before entering the dust-free workshop. However, before putting on the rabbit suit, we should first put on shoe covers, headcovers, beard covers, and cloth gloves.

This area is not completely dust-free, but it has adopted the same pressurized one-way ventilation system as the dust-free workshop: its air pressure is higher than that of the outside office area, and highly purified air is blown in from above and sucked away from below. In this way, all pollutants that may be floating in the air can be caught as soon as possible.

You must wear good hands, shoes and headgear before you can enter the next area to wear protective clothing Photo Source: Silicon via Intel

Then we went to the next area and put on a decent rabbit suit. The air pressure in this area is higher than the previous one, and the result is that the closer to the real dust-free workshop, the cleaner the air and the less pollutants. There are four rabbit suits: a hood, a jumpsuit, a shoe cover and latex gloves. Fellow travelers should also help each other to check whether the wear cover is complete.

Photo source: Silicon via Intel

Photo source: Silicon via Intel

But in fact, the rabbit suit does not protect us, but the equipment in the workshop and the wafer / chip itself.

These means of production are so sensitive to pollution that any particulate matter can scrap an entire silicon wafer. The whole Fab 28 works uninterrupted 364 days a year, 7 × 24 hours a year, and the output is huge. If the environment is not clean enough, even one minute of pollution exposure is enough to accumulate millions of dollars in losses. In turn, temporary suspension of work for cleaning and maintenance work will further expand the losses.

That's why Intel has such high requirements for cleanliness: no more than 1 particle per cubic meter (the operating room requires only about 30, 000).

Even all tools used in this area must be dust-free. The staff "confiscated" my notebook and sent me a set of paper and pens specially used in the dust-free workshop. Because they use special paper and ink, it is not easy to produce static electricity and fiber, particles fall off.

Photo Source: du Chen / Silicon Man

/ there are robots everywhere / after putting on the rabbit suit and being dust-free, we finally officially entered the dust-free workshop of Fab 28. The air pressure here is the highest in the whole building.

You may be able to see a little "yellowing" from the picture, because the entrance area is directly connected to the Litho department of the workshop. The general white light is actually a combination of many kinds of light, which will have an impact on the wafer, so the pure yellow light will be used in the lithography department:

Photo source: Silicon via Intel

As soon as we entered the workshop, we were surprised to find that less than a meter above our head, Daifuku robots were shuttling back and forth along the track.

The black "goods" carried by these robots are called FOUP-- front open unified processing boxes (Front Opening Unified Pod).

The role of FOUP is to transport valuable wafers between hundreds of devices with various functions in various areas and departments of the plant.

The robot grabs a FOUP with a robotic arm. Source: Silicon via Intel.

Maximum capacity of 25 wafers per FOUP Source: Silicon Star via Intel

The following two pictures are taken at the interface between the machine and the FOUP, and you can see that the robotic arms of both sides can cooperate with each other to grasp and place the wafers safely, ensuring that the impact on wafer quality during transportation is minimized:

Photo source: Silicon via Intel

Photo source: Silicon via Intel

The tracks FOUP runs, known internally as "automatic Super Highway" (ASH) within Intel, are spread throughout the workshop. Looking up at any "intersection", you can see at least seven or eight robots at a glance. How many FOUP are there in the whole factory? Intel did not answer, but revealed that there were "thousands".

It is worth noting that FOUP can not only run in the middle of dust-free and dusty areas, Intel is also building a larger fab Fab 38 next to Fab 28, when the two factories will also be connected by ASH orbits. a silicon wafer may be implanted at 28, then transported to 38 to finish lithography, and then shipped back.

Photo source: Silicon via Intel

/ A stroll through the dust-free workshop / the whole workshop covers an area of 4 American football fields, filled with all kinds of machines, and accomplishes all kinds of tasks. Only in the equipment that I can see with the naked eye, products from the world's five largest semiconductor equipment manufacturers, such as Yingsai, ASML and Tokyo Electronics, have gathered here.

In the course of the visit, the staff repeatedly reminded us: don't press the button, don't lean on the machine, or even don't even touch it. This is because the precision of chip production is extremely high, any accidental touch may produce vibration, or even machine displacement, resulting in production defects or machine failure. In fact, dozens of Intel wafer factories around the world, including Fab 28, are located in areas where crustal movement is relatively stable, and some high-precision machines in the workshop are also installed directly on shock-resistant panels.

Press the EMO button and emo. In fact, it means emergency manual overcontrol. Photo source: Linus Tech Tips

After watching the flying FOUP in front of us, we came to the defect response department at the next stop.

As long as the factory is running, the defect response department will not be off duty. Their job is to deal with various defects in the production process 364 days a year x 24 hours a year, to assess the causes of the defects, and if they have encountered them, to deal with them immediately using the measures that have been developed. If it is an unprecedented defect, then the field engineer will record the data, immediately organize a team to study the cause, and develop new countermeasures as soon as possible.

Shai Perets, an electron microscope engineer, introduces us to why the defect response team is called the "dream team" because the full name of this work is DREAM-defect reduction evaluation and methods (defect reduction Assessment and methods)-not only to detect defects, but also to design and develop methods and techniques to avoid defects and improve yield.

Photo source: Silicon via Intel

The working style of the engineer team in the whole plant is also quite special, which is usually divided into two groups: on-site and remote. Take the "Dream team" as an example, someone is in the downstairs workshop to collect data and complete the operation; there is also a special office in the command center of the office area upstairs. it is filled with a group of "omnipotent" engineers who know enough about the whole process of chip birth, responsible for defect analysis.

Intel likens these field engineers to "astronauts", while the engineers upstairs are "Houston ground Control Center".

The team photo of the command center of the defect response department source: Silicon via Intel

At the next stop, we came to the lithography department. At the workshop site, we saw the most advanced 36nm lithography machine known on the market at present. Batz Kleiz, an engineer, told me that the equipment used in the lithography department mainly comes from ASML, Tokyo Electronics and other enterprises. Each machine costs tens of millions of dollars, and considering the area of the workshop, there are four football fields. You can imagine how valuable the factory is.

Lithography Department of a fab Photo Source: Silicon Star via Intel

A set of assembly lines includes lithography, film, development and other functional machines, and wafers are passed back and forth between these machines. In most cases, the machines can be exchanged directly at the closed interface, and sometimes the aforementioned FOUP is used for "long-distance transfer" of the wafer.

Kleiz said that after years of lithography production process optimization, the production speed of the assembly line is now very fast. Although the exact number can not be disclosed, the entire Fab 28 lithography process has reached "four digits" per minute.

A robotic arm inside a device is moving the wafer. Photo Source: Silicon Man via Intel

Intel also wants to demonstrate what to do when the machine breaks down.

Intel Israel has a special talent program "Ofek Darom". Regardless of educational background and background, even farmers can "transfer" to chip engineers as long as they are studious, sincere and driven. But this also brings a problem, that is, every time a novice "goes out in the field", he needs an old master to bring new people, which is not only troublesome, but also expensive to learn.

In recent years, Intel has begun to use AR in many factories around the world, including Fab 28. Novice engineers wearing HoloLens head display, you can directly watch the AR tutorials on the scene, which will teach you where each tool is placed in the toolbox, how many turns a screw should be screwed, which button to press first, which button to press, and so on.

These AR tutorials and tools can be written by engineers themselves anytime, anywhere. Intel said that since the introduction of AR technology to assist in training, employees have been getting started much faster. At present, in the dust-free workshop alone, there are at least 150 engineers from the "Ofek Darom" project, who have completed the training in only three years and are able to do all the work on their own.

Photo Source: Linus Tech Tips

Because there are too many machines and they all look alike, the staff find it very easy to get lost in the workshop, and some maintenance work is very urgent and highly concentrated, so they will find the wrong machine and cause unnecessary losses.

So, in addition to numbering every road, every intersection and every machine in the workshop, Intel also added [color + animal] visual logos to the machines, such as "blue scorpion", "red rhino" and "green zebra". This effectively reduces the probability of engineers making mistakes when they work hard.

Photo source: Silicon via Intel

This is the end of the whole visit to the dust-free workshop. Let's show you some more photos from the workshop. After all, it's hard for ordinary people to get in:

Photo source: Silicon via Intel

Intel's pursuit of reducing defects and improving quality can be reflected in the following sentence: every grain of Every die wants to live-- wants to survive.

Photo Source: Linus Tech Tips

The following picture can pay attention to the green floor with holes on the ground. the whole dust-free workshop, including the supporting area, uses pressurized one-way air circulation: clean and dust-free air is ejected from above and sucked away from the floor, the closer the dust-free workshop is, the higher the air pressure is.

The system also operates 24 hours a day, 365 days a year, replacing the air in the entire workshop every 20 seconds.

Photo source: Silicon via Intel

Photo source: Silicon via Intel

The staff pretended to wipe the equipment, but the whole area was too clean to use at all. Photo source: Silicon via Intel

Lens in the device, recording part of the process during the birth of the chip Source: Intel

Photo source: Silicon via Intel

Employee aisle between different areas of the fab Photo Source: Silicon Star via Intel

After walking out of the dust-free workshop, we walked backwards and took off our protective equipment. This trip is not very hot, but it is a bit choking, mainly because the protective clothing, masks, glasses and latex gloves are airtight, because the equipment requires that the air conditioner in the workshop should not be too cold (28 °C).

So when I finally came out to take off the rabbit suit, the whole person breathed more smoothly-which made me admire the Intel employees who stayed in the workshop for most of the year.

It is worth noting that not only can the FOUP run in the middle of dust-free and dusty areas, Intel is also building an Fab 38 next to Fab 28, where the track will string the two factories together so that both FOUP and robots can travel back and forth.

Overlooking Fab 38 / as soon as we came out of the workshop, we were taken to the roof of the parking building next to us. Here you can see the Fab 38 site under construction next to it.

Fab 38, codenamed "Sparrow", is a new fab built by Intel next to Fab 28, with an area of about the same size ("still four American football fields"), but the overall technology is more advanced, costing more than $1 billion.

Because of the special roof design of Fab 38, an extremely large crane is needed to lift a steel frame that makes up the roof.

So Intel hired the Belgian lifting giant Sarens to assemble a SGC series giant crane on the Fab 38 construction site. It will be by far the second largest crane in the world, with hooks carrying an astonishing 2850 tons. (the largest is in Munich, and the customer is also Intel.) it takes at least a quarter to assemble the crane with four tower cranes.

Photo source: Silicon via Intel

Photo source: Silicon via Intel

And the whole project was so big and needed so much cement that Intel built its own cement plant directly next to the site.

Photo source: Silicon via Intel

Fab 28 represents Intel today, while Fab 38 will represent the future of the chip giant.

Upon completion, Fab 38 is expected to mainly use newer RibbonFET + PowerVia technology to replace the "outdated" FinFET transistor process for the production of future process products such as Intel 4, 3, 20A, and become one of the bases of the contract manufacturing service strategy IDM 2.0 promoted by the company in the past two years, so as to better serve contract manufacturing customers in Asia and Europe.

/ IDC Chip Test Lab / there was a serious shortage of semiconductor talent in the United States in the 1970s, and Intel recalled Dov Frohman, the company's early employee and inventor of EPROM technology, fulfilling his long-cherished wish of returning to his native Israel to set up a high-tech research center, allowing him to set up IDC in Haifa. At first, the word D stands for design (design), and then it was fully upgraded to R & D (development).

IDC building photo source: Silicon via Intel

In addition to Fab 28, another stop on my trip to Israel is the chip test lab in IDC. For Intel, chip testing is not about taking a random sample from the production line and putting it on the motherboard to see if it can be turned on-the whole testing process is very complex and demanding. And the company's target is that "every chip that leaves the factory must be tested" (the process is different).

For this reason, Intel has built a huge, labyrinth-like chip testing laboratory in the IDC building, including boot, verification, games, running scores, compatibility of peripherals, extreme environmental stability and so on. Even when the chip breaks down, there is a mysterious "chip operating room" with a group of engineers whose identities are kept secret to perform nano-scale minimally invasive surgery on the chip.

In addition, under the aforementioned IDM 2.0 strategy, Intel also provides testing services for Windows device brands, including Microsoft, Dell, Lenovo, etc., which are also carried out in the laboratory environment of IDC.

These tests are carried out not only by IDC employees, but also by designers and engineers from all over the world every time a new generation of chips is released.

A cat sleeps at the door of the building. Photo: du Chen / Silicon Man

IDC corridor photo source: Silicon via Intel

And then officially enter the chip test lab. Our first stop is opening the computer room (power-on room).

To put it simply, chip designers first make paper designs, then submit them to the fab for "proofing" and take weeks to months to produce ES1 (engineer samples) chips. After leaving the factory, the first step of the test sample is to turn it on.

Photo source: Silicon via Intel

Then there is the verification laboratory (validation lab). Here, Intel will further verify and test the subsystems of the chip (integrated graphics card, logic, memory, connectivity, compatibility).

Because Intel needs to run hundreds or even thousands of test machines here, the entire verification laboratory occupies a large area. The reason for this is that the testing work cannot be carried out on a random number of chips and must be carried out on a large scale.

Photo source: Silicon via Intel

Verify the source of the lab picture: Silicon via Intel

Photo source: Silicon via Intel

Verification testing will use some hard drives, memory, graphics cards that are on sale in the market. However, in order to better test the compatibility of the chip with the new technology that is not yet popular, the staff will also design some highly customized motherboards, PCIe analog cards, USB peripheral analog devices and so on.

For example, the motherboard used for testing is not sold in the market, but is designed by Intel, called "reference Verification platform" (RVP). Its functions and configurations can be achieved by remote control, and provincial engineers have to run around for debugging.

Another example is what looks a bit like a graphics card in the following picture: it is actually the first device to use PCIe 5.0. it is a FPGA (produced by Altera) designed by Intel test engineers to test the PCIe 5.0 compatibility of new chips (including 12 and the upcoming 13-generation Core).

FPGA for PCIe 5.0Photo Source: Silicon via Intel

You can think of this card as a "super simulator", which can simulate a variety of devices such as graphics card, storage, memory, network, etc., but its more important role is to monitor and record the control performance of the test object chip for PCIe 5.0devices. And because it is a FPGA, engineers can easily use DIP switches and reprogramming to quickly modify its functionality and performance-that is, adjust the variables in the test.

In addition to this FPGA card, Intel has also independently developed a lot of flexible test equipment. For example, to test video output, CPU integrated graphics cards need to support multiple monitors, but installing a bunch of monitors on each test bench in the lab takes up too much space, so Intel developed a device like a U disk, which can simulate the state of multiple monitors plugged into the motherboard.

The following thing is also saved by Intel itself, which specializes in testing the performance of various USB-C interfaces. As we all know, there are many USB versions, transport protocols and functions supported by C port, which are very confusing. It is common to buy the wrong cable / adapter. Intel wants to ensure that the chip works properly in as many cases as possible, so it has designed such a device that can simulate a variety of transmission protocols, daisy chains and so on.

Photo Source: Linus Tech Tips

And the following picture of the red pipe device: this is not what CPU fan / AIO and so on, its official name is hydraulic pneumatic cooling system (HPCS), can also be called heat pipe (thermal head), the role is to simulate a variety of possible temperature changes, such as cold start heating, hot start cooling, rapid hot quick cooling, etc., so as to ensure that the final chip in a variety of circumstances can maintain reliable performance.

Photo source: Silicon via Intel

Since it is a chip testing laboratory, what should I do if there is a problem?

The answer, of course, is to have it overhauled. The most important work is done in the underground debug laboratory.

Finally, we came to the debug laboratory. The task of the engineer here is to find out what the problem is based on the problem reported upstairs, identify the cause, and try to fix it in a variety of ways, and then give the repair results to the designer to modify the design of the chip.

A debug engineer told me that, in theory, if their designer colleagues are working seriously, they should be unemployed. However, this is not the case. On a grain the size of a nail cover, there may be dozens or even hundreds of designers, each responsible for a block. Between blocks, it is likely that the chip does not work properly because of the wrong order of circuits. "it's perfectly normal for us."

What's more, the probability of producing bug all year round is small, so the team of debug engineers is not large (there are only five people in the office that day).

Although the sparrow is small, it has all the internal organs. The debug department has the coolest equipment I've ever seen in the whole chip test lab.

The LADA machine on the right side of the picture can change the working principle of the chip with a high-power laser. Photo: Silicon via Intel

The first is the following machine, which is called LADA, the full name of "laser-assisted period change" (laser-assisted device alteration). For example, the debug team found that there was something wrong with a transistor in the chip and wanted to verify whether the modification proposal was effective-just put the chip under the machine and illuminate the pointing part of the chip with ultra-precision and high-power lasers, and you can change the properties of that transistor, thus changing the way the chip works.

LADA machine picture source: Linus Tech Tips

Photo Source: Linus Tech Tips

And if the laser can not completely solve the problem, the need for surgery on the chip, how to do?

I was taken into a more mysterious room:

Photo source: Silicon via Intel

The machine in the middle of the room is called FIB, or focused ion beam (focused ion beam). This machine is really an operating table for chips: it first cauterizes the encapsulated chip with a laser. Cut a micron-level "wound" in the cover, and then use FIB to make submicron "modifications" to the circuit on the chip.

Intel did not disclose how many FIB engineers the company has, except to say that operators who meet the technical operation level required by the company may be in the double digits around the world.

Photo source: Silicon via Intel

The following figure is an example: ion beams can build new bridges over tiny circuits, connecting misdesigned circuits in the right way. Physical modification of the chip with FIB technology can reduce the number of design modifications, accelerate the verification process, and finally shorten the chip development time and cycle, ensuring to meet Intel's 24-36-month research and development cycle of the first-generation chip deadline.

Photo source: Silicon via Intel

These are the records of the Silicon Man's visit to the Intel Fab 28 and IDC chip test labs.

The visit was part of Intel's Intel Technology Tour (ITT) in Israel and was attended by dozens of analysts from more than a dozen countries around the world. The ITT agenda also includes more new technologies and products such as the upcoming demo of the 13th generation of Kouri chips. In addition, last week we also wrote a report on Israeli science and technology creation environment and entrepreneurial culture, which you are welcome to read.

At the same time, readers are welcome to continue to follow the Silicon people. Next week, we will unveil a new cross-platform (computer / smartphone) software product developed by Intel.

More Fab 28 and IDC photos:

The 13th generation of Core in testing? ) Chip Picture Source: Silicon via Intel

Photo source: Silicon via Intel

Photo source: Silicon via Intel

Staff from third-party companies are testing the overclocking performance of the 13th generation of Kool. Photo Source: Silicon via Intel

We also saw Arik Shemer during the trip. He is a chip debug engineer who, like many early Israeli employees, "returned home" from the United States. He has been working for 44 years since 1978, but is only in the top 30 in the company's current employee years.

However, he is proud to say that Pat Gelsinger, a colleague and friend who often sends telegrams and e-mails (not email), is now the CEO of the company.

GYAT = get your acts together, one of Intel's "famous" corporate cultures. Photo source: Silicon via Intel

Photo source: Silicon via Intel

Photo source: Silicon via Intel

Photo source: Silicon via Intel

Photo source: Silicon via Intel

Photo source: Silicon via Intel

IDC Photo Source: du Chen /. Silicon man

Fab 28 Photo Source: Silicon via Intel

Photo source: Silicon via Intel

Photo source: Silicon via Intel

Note: the picture is from Intel and the copyright belongs to the original author. If you do not agree to use it, please contact us as soon as possible and we will delete it immediately.

This article comes from the official account of Wechat: Silicon Man (ID:guixingren123), Wen | Editor du Chen | VickyXiao

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