Shulou(Shulou.com)11/24 Report--

The emergence of Chiplet technology is the inevitable choice of the industrial chain under the demand of production efficiency optimization, and its technical core is to achieve high-speed interconnection between chips, so UCIe has not made strict restrictions on its members in the specific packaging methods, and two camps have been divided into two camps in the industry.

The wafer camp mainly interconnects the large area silicon intermediary layer, which can provide higher speed connection and better expansibility, while the packaging factory camp strives to reduce the wafer processing demand and put forward cheaper and more cost-effective solutions. Both wafer factories and packaging factories seek to obtain a higher proportion of industrial chain value in the era of Chiplet. In China, Changdian Technology launched TSV-less 's advanced packaging solution XDFOI, which leads the development of the industry; Tonfu Micro Power achieves high-speed growth through its excellent wafer-level packaging capability and binding to AMD.

Source Changjiang Securities "Chiplet Technology: advanced Packaging, who dominates ups and downs"

Author: Yang Yang, Zhong Zhiwu, Han Zijie

01. Efficiency optimization of heterogeneous Chiplet chips at the manufacturing level in fact, the original conceptual prototype of Chiplet came from Gordon Moore's 1965 paper "Cramming more components onto integrated circuits". In this paper, Gordon Moore not only proposed the famous Moore's Law, but also pointed out that "it is more economical to build large-scale systems with smaller functions, which are packaged separately and interconnected."

In 2015, Dr. Zhou Xiuwen, Marvell, put forward the concept of MoChi (Modular Chip, modular chip) at the ISSCC conference, laying the groundwork for the emergence of Chiplet. We believe that the development of modern information technology industry is not a process of exploring the unknown, but a demand-driven technology upgrade, and the emergence of Chiplet technology is the inevitable choice of the industrial chain under the demand of production efficiency optimization.

A device in which a computer can instruct and automatically perform any arithmetic or logical operation according to a series of instructions. In daily life, any electronic system we use can be regarded as a computer, such as computers, mobile phones, tablets and even microwave ovens, remote controls, etc., including the computer system as the core control equipment.

Chiplet is inseparable from two major trends:

1) the heterogeneity and integration of computer systems are getting higher and higher.

In order to understand why the industry must choose Chiplet, from the point of view of computer architecture, this report will first sort out an important development idea of computer architecture-heterogeneous computing. Like the modern economic system, in order to pursue higher output efficiency, the modern economic system has produced a very large and complex industrial division of labor system, and the re-division of computer system is heterogeneous computing.

The emergence of GPU and DPU is to make up for the shortcomings of CPU in graphic calculation and data processing, so that CPU can focus on logical judgment and execution, which is computer system (System). The fine division of labor also makes the whole system become huge, small computing devices can only integrate different chips into one chip, forming a SoC (System on Chip).

The concept of ▲ SoC (System on Chip)

As computers undertake more and more processing work in modern human life, the heterogeneous trend of computer architecture will become more and more obvious, and the chip area required will become larger and larger. At the same time, it also requires heterogeneous integration of chips such as power management IC and logic chips, while SoC as a separate chip, its area and processing methods are limited, so SoC is not the ultimate heterogeneous solution.

2) the problems of data path bandwidth and delay between chips have been solved by the industry.

The job of the chip is to execute instructions and process data. The interconnection between chips requires huge bandwidth and ultra-low delay. Since the area of a single chip cannot be increased indefinitely, it is a natural idea to disassemble a chip into multiple chips, manufacture them separately and then package them together. The interconnection between chips needs to build a strong data path, that is, ultra-high frequency, ultra-large bandwidth and ultra-low delay, which is also solved by the advanced packaging technology represented by TSMC CoWoS technology.

▲ provides 307GB / s high-speed bandwidth for chips based on advanced packaged HBM2.

In March 2022, Apple released the M1 Ultra chip, which uses the UltraFusion package architecture, through the internal interconnection of two M1 Max grains. Architecturally, M1 Ultra uses a 20-core CPU, which is composed of 16 high-performance cores and 4 energy-efficient cores. Compared with 16-core CPU chips with similar power consumption range on the market, the performance of M1Ultra is 90% higher. The high-speed interconnection of two M1 Max is the key to achieve the lead of Apple chips. Apple's UltraFusion architecture uses silicon intermediary layer to connect multiple chips, which can transmit more than 10000 signals at the same time, thus achieving interconnection bandwidth of up to 2.5TB / s low-latency processors.

▲ internal structure diagram of M1 chip. M1 Ultra is made by splicing two M1 Max.

In order to alleviate the "memory wall" problem, AMD's Ruilong 7 5800X3D desktop processor in its Zen 3 architecture is the first to use 3D stacked L3 cache, so that CPU can access up to 96MB L3 cache, greatly improving chip computing efficiency.

▲ AMD Zen 3 Chiplet

3) heterogeneous integration and high-speed interconnection have shaped the milestone of Chiplet.

To sum up, Chiplet itself is not a technological breakthrough, but a milestone shaped by many technological iterations and progress, and chip leading enterprises still have a say; therefore, Chiplet technology will not bring much direct impact and changes to the industry in the short term, but it will change the ecology of the global integrated circuit industry in the long run. At the same time, because Chiplet has mature technical support in many aspects, such as design, manufacture, packaging and so on, it will advance very quickly.

▲ Chiplet is the integration reduction of PCB and the deconstruction amplification of SoC.

Technology serves the demand, and the emergence of Chiplet alleviates the contradiction between the dependence of computing power on the number of transistors and the bottleneck of wafer manufacturing. As mentioned earlier, the requirements that lead to the emergence of Chiplet technology determine its impact on the industry. With the increasing demand for computing power in modern data processing tasks, in essence, the core of the improvement of computing power is the increase in the number of transistors.

As one of the founders of Intel, Gordon Moore pointed out in the initial model that the number of transistors on a single chip cannot increase indefinitely from a technical or cost point of view; therefore, while the industry is committed to increasing transistor density, it is also trying other software and hardware ways to improve chip efficiency, such as heterogeneous computing, distributed computing, and so on.

The relationship between the unit price of ▲ transistor devices and the number of transistors on a chip

Chiplet is an extension of heterogeneous computing, which mainly solves the problem of efficiency in chip manufacturing. With the indentation of the manufacturing process, the core

There are two major bottlenecks in chip manufacturing: 1) after 28nm, the transistor performance-to-price ratio of high-process chips is no longer improved; 2) the cost of chip design increases greatly, and the sunk cost of advanced process chip design is unacceptably high.

The manufacturing cost per million chips in each process of ▲ will not be reduced in the future for 28nm nodes.

The cost of ▲ advanced process chip design is rising rapidly (millions of US dollars)

About how Chiplet improves the efficiency of design and production, as well as its impact on EDA, IC design and other industries:

(1) based on the area advantage of small chips, Chiplet can greatly improve the yield of large chips, improve the utilization efficiency of wafer area and reduce the cost.

(2) based on the flexibility of chip composition, after Chiplet SoC, different core / core can be manufactured separately, and then packaged by advanced packaging technology, which does not need all advanced processes to be integrated on one wafer, which can greatly reduce the manufacturing cost of the chip.

(3) based on the reusability and verified characteristics of the small chip IP, the large-scale SoC is decomposed into modular core particles according to different functional modules, and the repeated design and verification links are reduced, which can reduce the design complexity and design cost, and improve the product iteration speed.

Compared with 32-core SoC, ▲ can greatly reduce the cost of chip manufacturing.

Although there is some optimization in the total manufacturing cost, because advanced packaging plays a more important role in the Chiplet manufacturing process, closed test enterprises may benefit deeply from the Chiplet trend. At present, a hundred flowers blossom in the field of Chiplet packaging. The core of Chiplet is to achieve high-speed interconnection between chips, while taking into account the re-routing of multi-chip interconnection. Therefore, the UCIe Alliance does not impose strict restrictions on its members on the specific packaging methods. According to the Chiplet white paper issued by the UCIe Alliance, the UCIe Alliance supports four mainstream packaging methods in the market, which are:

1) Standard package: the metal wires between chips are embedded in the package substrate. 2) the silicon bridge is used to connect the chip, and the silicon bridge is embedded in the packaging substrate, such as Intel EMIB scheme. 3) use silicon intermediary layer (Si Interposer) to connect the chip and rewire it, and then encapsulate the silicon intermediary layer on the substrate, such as TSMC CoWoS scheme. 4) use fan-out intermediary layer for rewiring, and use silicon bridge connection only at the chip connection, such as solar and moonlight FOCoS-B scheme.

Four Chiplet packaging methods recommended by ▲ UCIe Alliance

At present, with its advantages in wafer foundry, TSMC's CoWoS technology platform has served many customers and iterated over several batches, and is beginning to take shape: the core of TSMC's CoWoS platform is the silicon intermediary layer, and its production is mainly realized by etching TSV through holes on silicon wafers, and the technical difficulties are mainly to achieve the alignment of high aspect ratio through holes and high density pins. After the production of Die and Interposer, it is handed over to the packaging factory for packaging.

The technical core of Chiplet at the packaging level is as the interconnection between chips. The speed and delay of data transmission between chips are the key to technological competitiveness. At the same time, the stability and universality of the scheme will also have a profound impact on its long-term development space.

02. The global pattern of the two camps, competing to achieve Chiplet depends on advanced packaging technology is still not unified in the industry chain, mainly divided into wafer factory camp and packaging factory camp: wafer factory camp to wafer processing to achieve interconnection, can provide higher-speed connectivity and better expansion; packaging factory camp is trying to reduce wafer processing demand, put forward a cheaper, more cost-effective solution.

TSMC: integrate 3DFabric platform to realize rich topology combination. In terms of 2.5D and 3D advanced packaging technologies, TSMC has integrated 2.5D and 3D advanced packaging technologies into a "3DFabric" platform, which is freely matched by customers. The front technology includes 3D integrated chip system (SoIC InFO-3D), and the rear assembly test technology includes 2D / 2.5D integrated fan out (InFO) and 2.5D CoWoS series family.

▲ TSMC 3DFabric platform

In terms of 2.5D, TSMC offers two major solutions including CoWoS and InFO. Among them, CoWoS includes three packaging methods: CoWoS- S, CoWoS-R and CoWoS-L.

CoWoS-S uses silicon intermediary layer, and uses silicon wafer as intermediary layer to connect small chips. Compared with other schemes, the large area silicon wafer as the intermediary layer can provide higher density chip interconnection, but it is also more expensive.

▲ CoWoS-S architecture of TSMC

CoWoS-R uses organic adapter board to reduce cost, and its packaging scheme is the same as that provided by some closed test plants, and the interconnection density of organic adapter board is lower.

CoWoS-L uses a small silicon "bridge" inserted into an organic adapter board, and only silicon wafers are used in the interconnection part of the chip for high-density interconnection between the edges of adjacent chips. This interconnection is between CoWoS-R and CoWoS-S in terms of cost and performance.

In terms of InFO, after TSMC placed precisely (face down) on the temporary carrier, the chip was encapsulated in an epoxy "wafer", a redistribution interconnection layer was added to the reconstructed wafer surface, and the package bump was directly connected to the redistribution layer, mainly including InFO_PoP (mainly used for mobile platforms), InFO_oS (mainly used for HPC customers) and InFO_B (an alternative to InFO_PoP).

▲ InFO_PoP and InFO_B (bottom only) architecture of TSMC

▲ InFO_OS architecture of TSMC

TSMC's more advanced vertical chip stacking 3D topology package series, known as "system-on-a-chip" (SoIC), uses direct copper bonding between chips with smaller spacing.

▲ TSMC 3D chip stacking SoIC

Samsung: 3D IC packaging scheme strengthens the layout of Chiplet contract manufacturing industry. Samsung has started the research and development of packaging technology since 1990, and currently achieves the evolution of high-end packaging technology through SiP. The main technology trends are summarized as shown in the figure below.

The Historical Evolution of ▲ Samsung Electronics package layout

In August 2020, Samsung unveiled its X Cube 3D packaging technology (extended cube, which means expanding cubes). In the aspect of chip interconnection, the mature silicon through-hole TSV process is used. At present, X Cube has been able to stack SRAM chips on 7nm EUV logic chips produced by Samsung, which makes it easier to expand the capacity of SRAM and shorten the signal connection distance to improve data transmission speed and energy efficiency. After that, the release I-Cube places one or more logical die and multiple HBM die horizontally on the silicon intermediary layer for heterogeneous integration.

▲ Samsung Electronics 3D IC solution

Sun and Moonlight: FOCoS program strives to reduce silicon and reduce costs. Solar Moon's FOCoS provides a silicon bridge technology for small chip integration, called FOCoS-B (bridge), which uses tiny silicon wafers with routing layers as in-package interconnections between small chips, such as graphics computing chips (GPU) and high-bandwidth memory (HBM). The silicon bridge is embedded in the fan-out RDL layer, which is a 2.5D packaging scheme without using silicon intermediary layer.

FOCoS's silicon bridge provides ultra-fine pitch interconnection in the package, which can solve the memory bandwidth bottleneck challenge in the system. Compared with 2.5D packaging using silicon intermediary layer, FOCoS-B has the advantage of using silicon wafers in areas where only two small chips need to be connected together, which can greatly reduce costs.

▲ Solar Moonlight FOCoS solution

Amkor: deep layout TSV-less process. In terms of Amkor, the company launched SLIM and SWIFT solutions in 2015, and continued to carry out technology layout, with 2.5D / 3D TSV packaging capability.

▲ Amkor SLIM / SWIFT solution

The TSV-less process can be used to build advanced 3D structures. Both SLIM and SWIFT schemes adopt TSV-less process, which simplifies the PECVD and CMP processes when 2.5D TSV silicon intermediate layer is used.

Taking the SWIFT (Silicon Wafer Integrated Fan-Out Technology) scheme as an example, the scheme adopts RDL first technology, RDL linewidth and pitch capability ≤ 2um, μ bump pitch 40umSwift package can realize multi-chip integrated 3D POP package and HDFO high-density fan-out package without TSV (TSV-Less), which is suitable for high-performance CPU / GPU,FPGA,Mobile AP and Mobile BB.

The unique characteristics of 3D SWIFT are partly due to the small spacing function associated with this innovative wafer-level packaging technology. It makes the application of proactive design rules a reality, which is different from traditional WLFO and laminate-based packaging, and can be used to build advanced 3D structures to cope with the growing demand for IC integration in emerging mobile and web applications.

Changdian science and technology: domestic packaging leader, TSV-less route leading. Changdian Technology focuses on key application areas, and has industry-leading semiconductor advanced packaging technologies (such as SiP, WL-CSP, FC, eWLB, PiP, PoP and XDFOI series) and mixed-signal / RF IC testing and resource advantages in important fields such as 5G communications, high performance computing, consumer, automotive and industrial, etc., and achieves large-scale production, providing customized technical solutions for the market and customers.

The Historical Evolution of ▲ Changdian Science and Technology

The XDFOI solution is expected to be mass-produced by 2022H2, with higher performance, higher reliability and lower cost than 2.5D TSV,XDFOI. XDFOI is a kind of packaging technology based on 2.5D TSV-less. In design, this technology can realize 3-4 layers of high density wiring, and its linewidth / spacing can reach at least 2 μ m, and can realize multi-layer wiring layer.

In addition, the very narrow pitch bump interconnection technology is adopted, and the package size is large, which can integrate multiple chips, high-bandwidth memory and passive components. Changdian Technology has completed ultra-high-density cabling and started the customer sample process, and 2022H2 is expected to be in mass production, with emphasis on high-performance computing such as FPGA, CPU / GPU, AI, 5G, autopilot, intelligent medicine and so on.

Long Electric Technology's silicon-free through-hole fan-out wafer-level high-density packaging technology can use stacked through-hole technology (Stacked VIA) instead of TSV technology in the silicon intermediary layer (Si Interposer). This technology can realize multi-layer RDL rewiring layer, 2 × 2um linewidth spacing, 40um extremely narrow bump interconnection, and multi-layer chip superposition.

In addition, the very narrow pitch bump interconnection technology used by XDFOI technology can also achieve the package size of 44mm × 44mm, and support the integration of multiple chips, high-bandwidth memory and passive components. These advantages can provide solutions with high performance-to-price ratio, high integration, high density interconnection and high reliability for chip heterogeneous integration.

Technical characteristics of ▲ long Electric Technology XDFOI 2.5D

Advanced closed testing technology covers the 4nm process, breaking through the top domestic packaging process nodes. Changdian Technology announced in July 2022 that it has made a new breakthrough in the field of closed testing technology, realizing the packaging of 4nm process mobile phone chips, as well as the integrated packaging of CPU, GPU and RF chips. As an advanced silicon node technology, 4nm chip is also a part of Chiplet packaging. As one of the top technology products in the field of integrated circuits, it can be used in smart phones, 5G communications, artificial intelligence, autopilot, and high-performance computing fields including GPU, CPU, FPGA, ASIC and other products.

Tonfu micro-electric: binding AMD, wafer-level packaging to power Chiplet. The world's leading closed testing industry, advanced packaging cultivation of high-quality customers. Tong Fu Micro Power was founded in 1997 and listed on the Shenzhen Stock Exchange in 2007, mainly engaged in integrated circuit packaging and testing business. In 2021, Tonfu Micro potential ranks fifth in the global OSAT, and seventh in advanced packaging.

At present, the technical layout of the company is progressing smoothly, and it has begun mass production of Chiplet products, mass production of 7nm products in process nodes, and completion of research and development of 5nm products. Benefiting from the company's continuous efforts in closed testing technology, the company has established good cooperative relations with leading customers in AMD, NXP, TI, Infineon, ST, MediaTek, Zhanrui, Weir, Zhaoyi Innovation, Changxin Storage, Changjiang Storage, Jichuangbei and other domestic and foreign sub-sectors. Keep stable business ballast stone.

The Historical Evolution of ▲ Tongfu Micro Power

At present, the company has built the top 2.5D / 3D packaging platform (VISionS) and super-large FCBGA R & D platform, and completed the development of high-level digital rerouting technology.

Progress in Packaging Technology of ▲ Tonfu Micro Electric

For Chiplet, Tonfu Microelectronics provides wafer-level and substrate-level packaging solutions, in which wafer-level TSV technology is an important part of the Chiplet technology path. Most of the WLP wafer level packaging process is to package the wafer as a whole, and then cut it into pieces after the package is completed.

Wafer-level packaging encapsulates multiple bare wafers together in the form of shared substrate between chips, which is mainly used for high-performance large chip packaging. Using submicron silicon intermediary layer to integrate multiple chips into a single package with TSV technology, the material cost can be significantly reduced. Using non-carrier technology, after chip-to-wafer bonding and gap filling, the whole wafer is covered and flipped due to the exposure of back silicon holes. And directly maintained by epoxy model resin.

Core believes that in the post-Moore era, Chiplet has attracted wide attention because of its high performance, low power consumption, high area utilization and low cost, and is expected to continue the "economic benefits" of Moore's Law. In the post-Moore era, Chiplet chip design can lower the threshold of large-scale chip design, which brings great opportunities for the development of China's integrated circuit industry.

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