Shulou(Shulou.com)06/02 Report--

The MYD-CZU3EG development board launched by Mill Technology is equipped with a UltraScale+ MPSoC platform device-XCZU3EG, which integrates a four-core Cortex-A53 processor, a dual-core Cortex-R5 real-time processing unit, a heterogeneous processing system combining Mali-400 MP2 graphics processing unit and 16nm FinFET+ programmable logic, and has the characteristics of high performance, low power consumption and high expansion. in addition to this heterogeneous SOC, the board also carries rich interfaces and perfect development data. Let's take a look at it.

Open the box

The warm tone of the simple outer package is printed with the line "Make Your idea Real".

After opening the box, there are boards and supporting equipment placed in the lining. In addition to the board, supporting power, data lines, SD cards and optical discs, and so on, can be considered fully.

Introduction of board resources

The author can't wait to open the antistatic bag of the card. The MYD-CZU3EG development board consists of a MYC-CZU3EG core board and a MYB-CZU3EG backplane. Below the radiator is the core board, which is a CPU minimum system module that integrates the main processor and storage. The backplane is a peripheral interface board, which integrates power supply and a variety of interfaces to facilitate evaluation or integration.

First of all, the core board is based on Xilinx XCZU3EG fully programmable processor, 4-core Cortex-A53 (Up to 1.5GHZ) + FPGA (154K LE), specific model: XCZU3EG-1SFVC784 (future optional XCZU2CG, XCZU3CG,XCZU4EV,XCZU5EV), powerful performance; on-board 4GB DDR4 SDRAM (64bit 4GB DDR4 SDRAM 2400MHz) and rich storage resources to deal with complex operations calmly. On-board Gigabit Ethernet PHY and USB PHY, easy to achieve high-speed interconnection, such a luxurious configuration, the board size is only 62*50mm, amazing.

In addition, the board material selection and materials are exquisite, it is said that the use of Intel power module, Panasonic M6 PCB plate, Micron storage, Murata capacitor, or very conscientious.

The peripheral interface of the backplane is rich, including serial port, network port, HDMI,DP,SATA,PCIE,USB3.0 Type-C,LCD,PMOD,Arduino,FMC-LPC,TF card interface, SFP,ADC,CAN and other interfaces, which is convenient for users to evaluate or integrate. According to the structure of the SOC, some of these interfaces are connected to the PS terminal and some to the PL terminal.

PS module:

1 way Gigabit Ethernet 1 Road USB3.0 typeC Interface 1 Road DisplayPort Interface 1 Road PCIE2.1 x1 Interface 1 Road SATA3.1 Interface 1 Road CAN Interface 1 Road RS232 Serial Port 1 Road TF Card Interface 1 Road I2C Interface 1 reset button, 2 user buttons, 1 Road JTAG built-in real-time clock

PL unit: XADC interface 1 way Xilinx standard LPFMC interface 1 way HDMI interface, RGB 24bit, does not support audio 1 way LCD DIP/LPC interface, RGB 24bit, and HDMI multiplex display signal resistive capacitive touch screen interface, integrated in LCD touch screen interface 2 ways PMoD5 power indicators 4 ways SFP module interface 1 way Arduino interface

In addition to the board, the CD in the kit includes user manuals, usage examples, PDF backplane schematics, extended interface drivers, BSP source packages, development tools, etc., providing developers with a perfect software development environment.

However, notebook computers now rarely have CD-ROM drives, and copying these materials has really wasted the author's efforts. It is more convenient for manufacturers to replace them with USB drives to install data.

Zynq UltraScale+ MPSoC introduction

1. Real fully programmable heterogeneous multiprocessing SOC

Before using the board, let's take a look at the core chip of this board-XCZU3EG, which is the true fully programmable heterogeneous platform introduced by Xilinx after the ZYNQ-7000 series. Zynq ®UltraScale+ MPSoC devices not only provide 64-bit processor scalability, but also combine real-time control with software and hardware engines to support graphics, video, waveform and packet processing. On a platform that includes universal real-time processors and programmable logic, three different variants include dual application processors (CG) devices, quad-core application processors and GPU (EG) devices, and video codec (EV) devices, creating unlimited possibilities for 5G wireless, next-generation ADAS and the industrial Internet of things.

The MYD-CZU3EG development kit is currently equipped with EG, and CG or EV devices can be selected later. The EG device uses a quad-core ARM ®Cortex-A53 platform with a running speed up to 1.5GHz, a dual-core Cortex-R5 real-time processor, a Mali-400 MP2 graphics processing unit and 16nm FinFET+ programmable logic.

The board features unparalleled integration, high performance and low power consumption. Compared with Zynq-7000 SoC, the system-level performance and power consumption ratio is 5 times higher, and it is carefully designed to deliver the lowest system power consumption. Typical official applications include baseband L1 acceleration, public safety and mobile radio, and 8x8 100MHz TD-LTE remote RF unit scenarios.

The ideal system of multimedia

When it comes to applications, I have to mention what Zynq UltraScale+ MPSoC is best at-cutting-edge multimedia solutions for video codecs and graphics engines. Cyrus SoC provides a variety of support for multimedia solutions, including:

Integrated video codec unit (VCU) integrated graphics processing unit (GPU) with integrated DisplayPort interface module integrated programmable logic (PL)

EV device with integrated GPU and H.264 / H.265 video codec, specially designed for ultra high definition (UHD) video with integrated H.264 / H.265 video codec, can simultaneously encode and decode 4Kx2K (60fps) video, can achieve single-chip 4K video processing, of course, MYD-CZU3EG development board uses EG devices, there is no video codec, but there is Mali-400 MP2 GPU.

Mali-400 MP2 GPU binds directly to APU and accelerates video graphics rendering in the frame cache for display output. GPU can render pixels through a separate parallel engine, which is much faster than relying on CPU to process graphics, and has lower cost and power consumption than solutions that require designers to add an off-chip GPU engine. GPU accelerates 2D and 3D graphics with a fully programmable architecture that supports both shader-based graphics API and fixed-function graphics API. With anti-aliasing, GPU achieves the best image quality with almost no additional performance loss. Xilinx provides a full set of Linux drivers that have been tested in practice, which can automatically transfer graphic commands from APU to CPU.

In addition, Zynq UltraScale+ MPSoC provides high-speed interconnection peripherals, which include integrated DisplayPort interface modules. The DisplayPort interface is located on the PS side and can be multiplexed to two of the four dedicated high-speed serial transceivers at speeds up to 6 Gb/s. The architecture gets rid of the need for additional display chips and further reduces the BOM cost of the system.

The DisplayPort interface is developed based on VESA DisplayPort Standard Version 1 and Revision 2a. It provides multiple interfaces that can handle real-time audio and video streams from PS or PL, as well as store audio and video from memory frame buffers. It also supports two audio and video pipelines and supports dynamic rendering of alpha mixing, chroma resampling, color space conversion and audio mixing. DisplayPort can use either a PS PLL or a PL clock to generate a pixel clock.

In addition to video codecs and graphics processing, multimedia applications also need other important components, such as the input and output management of video data, and the function of processing high-speed video data. Customization logic can be designed within PL to capture video from live sources. For example, protocols such as SDI RX, HDMI RX, MIPI CSI IP, etc., can be used to capture raw video from different sources. Visual algorithms can be used to collect important information from the original data, such as road sign recognition and motion detection for driver assistance technology, video surveillance facial recognition, object and motion recognition for advanced shooting applications, and so on. In addition to collecting data, the algorithm can also be used to process and manipulate raw data in use cases such as audio and video broadcasting and video conferencing. Considering the inevitable rising trend of video resolution in the next few years, the relevant algorithms need to have a very high working speed. PL provides the required hardware acceleration for such algorithms to greatly improve performance and meet the needs of the next generation of technologies.

Zynq UltraScale+ MPSoC's flexible performance accelerates compute-intensive applications, shares workloads among GPU, CPU, and PL, unloads complex arithmetic calculations in PL for hardware acceleration, and pre-calculates OpenGL shading language (GLSL) consistent variables on APU. Calculations on the GPU shader core apply only to values that differ between vertices and fragments. All values that hold constants in a batch of vertices are most efficient on CPU.

Unparalleled ratio of system performance to power consumption

Zynq UltraScale+ MPSoC was designed with efficient power management in mind, and the device is divided into four power domains:

The battery power domain in the processing system (PS) contains a real-time clock and a battery-powered RAM. The low power domain in PS includes RPU, general peripherals, on-chip memory (OCM), platform management unit, and configuration security unit. The full power domain in PS contains APU, high-speed peripherals, system memory manager and DDR controller programmable logic (PL) in its own power domain.

The Zynq UltraScale+ MPSoC contains an innovative platform Management Unit (PMU) that can control the power domain. PMU is responsible for the safety management of devices and supervises the power supplies in the power domain. Unused power domains can be turned off at startup and then intelligently awakened by interrupts or events for fine power management.

We already know that there are multiple processing cores in Zynq UltraScale+ MPSoC. Quad-core ARM Cortex-A53 is an application processing unit with efficient baseline performance and is suitable for Linux application processing. Dual-core ARM Cortex-R5 is an ideal real-time processing unit for deterministic applications with low latency, such as security modules and APU task sharing. In addition, graphics engines and high-speed peripherals are optimized for specific applications. Each module does its own job, and the system performance is significantly improved. The device adopts the 16nm FinFET process node of TSMC. The process node uses a more efficient transistor implementation scheme, with the best switching speed and lower leakage current than the planar process, so it can achieve higher performance and lower power consumption. From the Zynq-7000 of 28nm to the Zynq UltraScale+ MPSoC of 16nm, the performance is improved by 60%, the power consumption is reduced by 20%, and the performance of the original processor is improved by 2.7%.

Example

Board QSPI flash memory pre-burned Linux image, the default is also started from QSPI flash memory, using data cable to connect the board serial port and PC, connect power, board power on, open putty, you can see the system boot information. You can log in from the command line, and the default password is root.

The image file of the system is also provided on the CD, and users can use it directly if they are not familiar with the compilation of the Linux system.

In addition, demo programs for common peripherals are provided on the MYD-CZU3EG CD, such as:

Use the LED on the Linux API operation development board using the keys on the Linux API operation development board using the CAN on the Linux API operation development board to carry out network communication programs using Linux API and the source code are located in "/ Examples/", users can compile according to the Makefile in the directory.

Here we use Xilinx Vivado to create a new HelloWorld project, generate a boot image, and launch it from the TF card. The whole process is divided into:

The hardware platform that generates the development board exports the hardware platform to SDK to create a "HelloWorld" project to generate Boot Loader (fsbl) to generate SD card boot image, boot from microSD

The core board of MPSoC platform Development Board (MYD-CZU3EG) has strong performance configuration and compact and reliable design, and the interface resources of external backplane are rich. The software development environment provided by manufacturers for developers is also relatively perfect, which is very suitable for prototype development in artificial intelligence, industrial control, embedded vision, ADAS, algorithm acceleration, cloud computing, wired / wireless communications and other application fields.

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