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Analysis of plic and eclic in riscv

1.PLIC interrupt processing

Programming Model of 2.sifive interrupt

3. About eclic

4. About jalmnxti

1.PLIC interrupt processing

In the RISC V architecture, there are some definitions of interrupts, so let's analyze the implementation strategy of this definition.

A total of three state interrupts are defined in riscv. For the hart level, hart includes local interrupt sources and global interrupt sources. There are only two kinds of local interrupts: Timer and Software interrupts, while global interrupts are called external interrupts. Only the global interrupt source can be responded to by the PLIC core, which is usually the Imax O device.

Generally speaking, timer and software are handled through CLINT (CORE LOCAL INTERRUPT), while external interrupts are handled through PLIC.

You can take a look at the processing flow of the hummingbird processor. In addition, the interrupt of sifive E31 is also handled as follows.

Programming Model of 2.sifive interrupt

The interrupt handling process has the following flow

First, the MIE domain of mstatus is copied to the MPIE of mstatus, and then the MIE domain of mstatus is cleared. At this point, disable is interrupted globally. The current PC value of the program is copied to the mepc register, and then the PC value is set according to the value of mtvec. If the vector interrupt is enabled, the PC value becomes the code at mtvec.BASE+4xexception. Get the state of the privileged mode from the mstatus.MPP

The next step is to handle the interrupt specific function implementation.

Set the state of privileged mode to mstatus.MPP, copy the data of mstatus.MPIE to mstatus.MIE, take values from mepc to pc.

Finally, execute eret to return to the normal running state of the program.

For CLINT, there are Software Interrupt and Timer Interrupt, which can be controlled directly in registers.

PLIC can actually be understood as the interrupt controller of arm, which has its map address.

Because the use of PLIC is for external interrupts, you can set each interrupt individually. You can set the following values:

Priority of interrupts priotity interrupt suspend bit pending interrupt enable enables interrupt threshold priority Thresholds

Because the implementation of PLIC is independent of hart's IP design, its design and layout are not necessarily identical.

3. About eclic

The design of eclic is an interrupt handling method designed by Xinlai Technology.

Eclic is also the interrupt controller used by many Xin Lai Technology core, including gd32vf103 series chips.

Interrupt No. 3 is a software interrupt generated by the kernel TIMER unit.

Interrupt 7 is a timer interrupt generated by the kernel TIMER unit.

The interrupt numbers from 1919 to 4095 are all external interrupts, and the interrupt number has nothing to do with the priority of the interrupt.

For the register layout of ECLIC, you can see the figure above.

Cliccfg is an interrupt global configuration register, which can be configured with clicinfo and data in global registers. For use, the threshold level register clicintip [I] of read-only mth interrupts is an interrupt wait register, which is also equivalent to the pending register clicintie [I]. For interrupt enable registers clicintattr [I], you can set the rising edge trigger or falling edge trigger of the interrupt. You can also set whether the interrupt slave is a vector interrupt or a non-vector interrupt. Clicintctl [I] sets the interrupt priority level and priority, which needs to be set with cliccfg. 4. About jalmnxti

This is also a custom instruction for eclic to speed up the tail-biting of interrupts in order to reduce interrupt latency.

The instruction is designed with eclic processing mechanism and has many functions.

Turn on interrupt enable, process the next interrupt and return to the next interrupt entry address to jump to interrupt handler interrupt processing and return

Because one instruction of csrrw ra, CSR_JALMNXTI, ra can achieve the effect of JAL (Jump and Link), and the hardware updates the Link register as the PC of the instruction as the return value of the function call, so after returning from the interrupt service program, it will go back to csrrw ra, CSR_JALMNXTI, ra instruction to execute again, you can re-judge whether there is an interrupt pending, if so, jump to the interrupt handling function, thus realizing the tail-biting processing of the interrupt. If you don't interrupt the wait, jalmnxti won't actually do anything.

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