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This article mainly introduces "what is the use of virtual class". In daily operation, I believe many people have doubts about the use of virtual class. The editor consulted all kinds of materials and sorted out simple and easy-to-use methods of operation. I hope it will be helpful for you to answer the doubts about "what is the use of virtual class?" Next, please follow the editor to study!

Class in SystemVerilog can have data members (data or properties) and methods (method).

The method in SystemVerilog class can be function or task. Usually, method that does not consume simulation time uses function, and method that consumes simulation time uses task.

Virtual class adds the virtual keyword before the class declaration to define a purpose-specific template class, that is, to define the prototype that the extension class needs to implement.

You need to implement the methods in virtual class in the extension class.

Virtual class was unable to create the corresponding object (object). Trying to construct an object (object) of virtual class using the constructor new () will give you a compilation error

Most of the class libraries defined in the UVM class library are virtual class, and almost all user-defined UVM authentication platforms are built on user-defined classes, which are extensions of UVM component classes. For example, all user-defined transactions are extension classes of uvm_sequence_item virtual class, and all user-defined sequence are extension classes of uvm_sequence virtual class.

The UVM base class library is a set of template files that users extend to build a UVM authentication platform.

For the following example:

Module test; virtualclass A; virtual function void my_display (); $display ("PROTOTYPE"); endfunction endclass classB extends A; virtual function void my_display (); $display ("help from B") Endfunction endclass An aura; B baugh; initial begin bauh = new (); b_h.my_display (); ahumh = new (); a_h.my_display (); endendmodule

Questasim simulation results:

# Hello! From B # * * Fatal: (vsim-8250) Class allocator method 'new' called on Abstract Class.

Reference:SystemVerilog Virtual Classes, Methods,Interfaces and Their Use inVerification and UVM

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