Shulou(Shulou.com)06/02 Report--

We have learned the syntax of variables and functions in makefile before, so today we will take the actual requirements as an example to actually write. Practical requirements: 1, automatically generate target folder to store executable files; 2, automatically generate objs folder to store compiled object files (* .o); 3, support debug version of the compilation option; 4, consider the expansibility of the code.

So before writing today's makefile, we need to know the following points of knowledge: a > $(wildcard _ pattern), which is used to get a list of files or directories that meet _ pattern in the current working directory; b > $(addprefix _ prefix,_names), which adds the prefix _ prefix to each name in the name list _ names.

The key skills: 1, automatically get the list of source files under the current directory (function calls): SRCS: = $(wildcard * .c); 2, generate a list of target files based on the list of source files (replacement of the value of variables): OBJS: = $(SRCS:.c=.o); 3, add a path prefix to each target list (function calls): OBJS: = $(addprefix path/, $(OBJS)).

Let's look at the pattern substitution (directory structure) in the rules, as follows

Look at the dependencies of the compilation rules, as follows

Let's take a look at how the specific makefile is written, or using the previous three .c files as the source files.

CC: = gccMKDIR: = mkdirRM: = rm-rfDIR_OBJS: = objsDIR_TARGET: = targetDIRS: = $(DIR_OBJS) $(DIR_TARGET) TARGET: = $(DIR_TARGET) / hello-makefile.out# main.c func.c const.cSRCS: = $(wildcard * .c) # main.o func.o const.oOBJS: = $(SRCS:.c=.o) # objs/main.o objs/func.o objs/const.oOBJS: = $(addprefix $(DIR_OBJS) / $(OBJS)). PHONY: rebuild clean all$ (TARGET): $(DIRS) $(OBJS) $(CC)-o $@ $(OBJS) @ echo "Target File = > $@" (DIRS): $(MKDIR) $@ $(DIR_OBJS) /%. C ifeq ($(DEBUG)) True) $(CC)-o $@-g-c $^ else $(CC)-o $@-c $^ endifrebuild: clean allall: $(TARGET) clean: $(RM) $(DIRS)

Let's take a look at the compilation effect.

We see that it has been executed correctly and two folders objs target are automatically generated under the current directory. Generate three .o files in the objs folder, generate the hello-makefile.out file in the target folder, execute the executable file, and the result is also what we defined earlier. Let's see if we can define the DEBUG version of the program, then we need to use a command objdump-S target, which is used to see if the program is a debug version. Let's take a look at the results. Figure an is the normal version, and figure b is the DEBUG version.

Figure an ordinary version

Figure b DEBUG version

We see that the DEBUG version has a few more things than the ordinary version, such as the printf statement we wrote in it, and more statements for function calls. The ordinary version only executes the program and then OK. Through the preparation of today's comprehensive example, the summary is as follows: 1, the directory can become the target of the dependence, create a directory in the rules; 2, the predefined functions are an indispensable part of makefile actual combat; 3, the rules of pattern matching can be directly for the files in the directory; 4, you can use command line variables to compile a special target version.

Welcome to learn makefile language, you can add me QQ:243343083.

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