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This article will explain in detail how to set input delay constraints in the development of big data. The editor thinks it is very practical, so I share it with you as a reference. I hope you can get something after reading this article.

This is a classical timing analysis model, the upstream chip sends the clock to FPGA, the internal synchronization components can be constrained by create_clock, the external chip sends data to the first level of FPGA through the FPGA port and the flip-flop is constrained by set_input_delay, and the last flip-flop of FPGA is constrained by set_output_delay. The combinational logic from the input port to the output port is constrained by set_max_delay.

In the figure, trace_delay refers to board-level delay, and input delay refers to the time input_delay it takes for the upstream chip clock to send data to FPGA to receive data.

Input_delay = Tco (clock output) + TD (trace delay)

The maximum delay can build the establishment time constraint, and the minimum delay can build the hold time constraint.

Constraints of DDR: sampling data on both rising and falling edges

Set_input_delay 1-min-clock clk [get_ports data_in]

Set_input_delay 2-max-clock clk [get_ports data_in]

Set_input_delay 1-min-clock clk [get_ports data_in]-clock_fall-add_delay (add_delay is required to prevent the statement from overwriting the previous statement)

Set_input_delay 2-max-clock clk [get_ports data_in]-clock_fall-add_delay

Set tco_max 2,0

Set td_max 3.0

Set tco_min 0.0

Set td_min 0.0

Create_clock-name sysclk-period 10 [get_ports clkin] / / create a system clock

Set_input_delay-clock sysclk-max [expr {$tco_max+$td_max}] [get_points din]

Set_input_delay-clock sysclk-min [expr {$tco_min+$td_min}] [get_points din]

This is the end of the article on "how to set input delay constraints in big data's development". I hope the above content can be of some help to you, so that you can learn more knowledge. If you think the article is good, please share it for more people to see.

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