How to use Verilog Basics

This article introduces the relevant knowledge of "how to use Verilog Basics". In the operation process of actual cases, many people will encounter such difficulties. Next, let Xiaobian lead you to learn how to deal with these situations! I hope you can read carefully and learn something!

Always Blocks

As its name suggests, the always block executes always, unlike the initial block, which executes only once at the start of the simulation.

The always statement block also has a sensitivity list that tells the always statement block when to execute the code block.

always @ (a or b or sel)begin y = 0; if (sel == 0) begin y = a; end else begin y = b; endend

The @ symbol is followed by the condition triggered by the always statement block. Only variables of type reg can be driven within the always statement block.

The above example is 2:1 mux, inputs a and b; sel is the select input, and y is the mux output.

In any combinational logic, whenever the input changes, the output changes. This means that the code in the always statement block is executed whenever the variables contained in the sensitive list change, i.e. a, b, and sel.

There are two types of sensitivity lists: level sensitive (for combinational circuits) and edge sensitive (for flip flops). The code below is the same 2:1 Mux, but the output y is now the flip flop output.

always @ (posedge clk )if (reset == 0) begin y