Shulou(Shulou.com)06/01 Report--

This article introduces the relevant knowledge of "how to implement the NAND FLASH controller". In the operation of actual cases, many people will encounter such a dilemma, so let the editor lead you to learn how to deal with these situations. I hope you can read it carefully and be able to achieve something!

Storage organization form

There are 2048 Block (blocks) in K9F2G08X0A, each Block contains 64 Page (pages), each Page contains 2k byte normal storage space and 64 byte check space.

Total space = 2048 * 64 * (2 * 1024 + 64) byte

Actual storage space = 2048 * 64 * 2 * 1024 byte

two。 Definition and connection of pins

3. Addressing mode

Column addresses: for Block and Page addressing

Line address: addressing within Page

4. Command

The following are several command operation instructions. For more commands, please refer to the chip manual.

(1) Read ID

Note: first send 0x90 and then send 0x00, and then nand flash will return 5 pieces of data, which varies according to the chip model. The specific values can be found in the manual.

(2) Page Read

Note: first send 0x00 and then send the address of the data to be read, and then send 0x30. According to 0x30 B, you can judge whether the transmission is complete. After the command is sent, it starts from the first falling edge of the RE, and the chip will output all the data from that address to the end of the page.

(3) Page Program

Description: first send 0x80, then send address and data, then send 0x10, read R B, send 0x70 after the command is completed, and then judge whether the write is successful according to I/O0. 0: success 1: failure

(4) Block Erase

Note: first send 0x90, then send line address 1 / 2 / 3, then send erase command 0xD0, judge whether the erase operation is completed according to the Rhand B pin, and then send 0x70 to judge whether the erase is successful or not according to the status of the I/O0. 0: success 1: failure

Note 1:

/ * initialize NAND Flash * / void nand_init (void) {# define TACLS 0#define TWRPH0 3#define TWRPH1 0 / * to determine whether it is S3C2410 or S3C2440 * / if ((GSTATUS1 = = 0x32410000) | | (GSTATUS1 = = 0x32410002)) / / 2410 {nand_chip.nand_reset = s3c2410 roommates; nand_chip.wait_idle = s3c2410_wait_idle Nand_chip.nand_select_chip = s3c2410 cycles and optional selectchips; nand_chip.nand_deselect_chip = s3c2410 cycles and optional deselectchips; nand_chip.write_cmd = s3c2410 writeboxes cmd; nand_chip.write_addr = s3c2410 writeboxes addr; nand_chip.read_data = s3c2410_read_data / * enable NAND Flash controller, initialize ECC, disable chip selection, set timing * / s3c2410nand-> NFCONF = (1)

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