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What this article shares with you is about the challenges and solutions of synchronization and allocation in big data's asynchronous reset network. The editor thinks it is very practical, so I share it with you to learn. I hope you can get something after reading this article. Without saying much, let's take a look at it with the editor.

The lack of coordination between asynchronous reset and synchronous clock can lead to design failure.

In VLSI design, asynchronous reset is used to reset the synchronous circuit to a known state after power up. This problem can worsen in large-scale multi-clock domain design.

In addition to synchronous (synchronization) issues, asynchronously resetting to millions of triggers in the design (distribution) is also challenging and requires techniques similar to CTS (clock tree synthesis).

Asynchronous reset challenges

Synchronous reset requires a valid clock, which may affect the timing of the data path. The synchronous reset is deterministic and will not lead to metastability.

Asynchronous reset does not require a valid clock, and special triggers that do not affect the timing of data paths can be used to input pins. However, an asynchronous reset may cause metastability in the trigger.

In many cases, an asynchronous reset can be replaced by a synchronous reset, but in some cases an asynchronous reset must be used. For example, when powered on, there is no clock or gated to reduce power consumption, but need to provide a known state for its external interface.

During the asynchronous reset setting, the timing between the clock and the reset can be ignored, but the asynchronous reset release must be synchronized with the clock. If the asynchronous reset is released at the edge of the clock, it may lead to metastability.

The high-level and effective asynchronous reset is shown in the figure above. Reset to the time a position, and affect the output Q of the trigger after the determined propagation delay TR-pd, and do not care about the state of the clock at this time. The reset is released at time b, and the RST port must meet the recovery and removal time (recovery and removal timing) relative to the clock port CLK, otherwise the trigger will become metastable, which may lead to design failure. This situation is similar to violating the establishment and hold time of trigger data port D.

In addition, for large designs, the skew of the reset and clock distribution network (reset and clock distribution networks) may be large due to unequal wire length, load, and IR drop and process deviations in the design. In this case, different parts of the design may be reset in different clock cycles, thus not achieving the desired function.

In the figure above, RESET arrives at triggers Q0 and Q1 in different clock cycles, causing the trigger to reset and release in different clock cycles.

In order to avoid the above problems, the release of the asynchronous reset must be synchronized to the target clock. The traditional scheme is to use a reset synchronizer at the root of the reset distribution network. As shown in the following figure

As shown in figs. An and b, the input asynchronous reset RSTI signal is connected to the synchronizer output RSTO through combinational logic. Therefore, the setting of RSTO does not depend on the clock.

In the synchronizer of figure a, both RSTI and RSTO are high-level effective signals, while in the synchronizer of figure b, the input RSTI_N is low-level effective signal and RSTO is high-level effective signal. When the RSTI is released asynchronously, it is synchronized by a two-level trigger (F0MagneF1). The RSTO is then released synchronously.

The operation of the reset synchronizer is shown in the waveform of fig. E. In synchronization, because the F0 flip-flop may be metastable, the delay of reset release may have a clock cycle change. The number of triggers used in the synchronizer should be set according to the MTBF calculation. Because the RSTI rate is very low, in most cases, two triggers can provide a satisfactory MTBF.

Figures c and d show another common style of asynchronous reset synchronizers. The trigger with asynchronous reset / set port is used, and the previous synchronizer uses a simple D flip-flop without RST / SET port. Figure c when RSTI is set, the output of the synchronizer RSTO_N (low level effective) becomes valid asynchronously regardless of the clock. When RSTI is released, the D port of trigger F0 is connected to the VDD signal ("1"). However, F0 may become metastable because the input of F1 does not change at the edge of the first clock, and F1 is not affected by metastability. Therefore, the constant "1" input is synchronized using a dual trigger synchronizer, resulting in a synchronous release of the RSTO_N.

The synchronizer of figure c and figure d can work without a clock, that is, the clock can appear after the RSTI is released. Before the RSTI is released, the synchronizers of figures an and b need a stable clock to initialize the internal trigger before the reset is released.

Figure f shows the reset path between the synchronizer trigger F1 and the target application trigger F2. As you can see, since both flip-flops F1 F2 are located in the same clock domain, the path TR should be optimized according to STA, that is, it should be shorter than the clock cycle and satisfy the recovery and removal time checks for all purpose triggers, such as F2.

The reset allocation network delay is expressed as TR, the clock cycle is represented as TCLK, and the design should satisfy the following expression (ignoring clock deviation):

TCLK > = TR+ TSU... (1)

Obviously, the timing convergence of the reset distribution network is challenging in the following cases:

Large reset distribution network. At that time, when the number of triggers in the clock domain is large, the reset allocation network path delay time TR becomes larger, which may be larger than a single clock cycle, so it violates the timing constraint (1).

High-speed clock rate. When a fast clock is used, the clock cycle TCLK becomes shorter, and timing convergence (1) is challenging.

High-performance designs with a large number of triggers that operate at high frequencies require special solutions for dealing with reset distribution networks. Optimization according to expression (1) requires an optimization algorithm similar to clock tree synthesis (CTS, Clock Tree Synthesis).

The main difference between CTS and reset tree synthesis is that reset tree synthesis lacks low skew requirements, as long as the constraint (1) is satisfied.

For ASIC design, this approach consists of a large number of large buffer. In FPGA design, global net resources are required.

Reset tree synthesis requires additional power consumption during reset handover. Considering that asynchronous resets are rarely used-they are usually used every time they are powered on. The power consumption, area, routing resources and run time of EDA caused by high fan-out global network are all unnecessary costs.

In order to satisfy the timing of the high fan-out network, the synthesis tool tends to copy the source trigger in the path to reduce the fan-out of the replicated trigger. Although this method is functionally correct for conventional synchronous logic, when considering asynchronous reset network, it may lead to functional failure and reduce the reliability of asynchronous reset network.

As shown in the above figure, the reset synchronizer is copied in fig. A. The global reset network is divided into two subnetworks, which contain {F1Magi F2} and {F1dMagneF3} paths respectively.

RSTI asynchronous inputs are synchronized by two different synchronizers, each of which produces random delays. Therefore, even if the RSTI changes at the two synchronizer inputs at the same time, the RSTO and RSTOd outputs can be separated by one clock cycle, resulting in the trigger F2 and F3 not being reset and released synchronously.

In a multi-clock domain design, asynchronous resets should be synchronized by each clock domain respectively, as shown in the figure above. Because different clock domains contain different numbers of triggers, their reset allocation network delays are not equal.

Each reset synchronizer generates additional non-deterministic delay, so it becomes impractical to design simultaneous reset release in the entire multi-clock domain.

The reset release sequence can be defined to ensure the correct reset operation. For example, the reset of the M2 module is after the M1 module is reset, and then M1 begins to send data to M2.

These are the challenges and solutions of synchronization and allocation in big data's asynchronous reset network. The editor believes that there are some knowledge points that we may see or use in our daily work. I hope you can learn more from this article. For more details, please follow the industry information channel.

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