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EXOSTIV waveform debugger provides an example analysis of innovative debugging for FPGA. I believe that many inexperienced people are at a loss about this. Therefore, this paper summarizes the causes and solutions of the problem. Through this article, I hope you can solve this problem.

FPGA debugging is an indispensable important link in electronic system design, the process involves a variety of technologies and tools, and the key task of engineers is to choose the right technology to achieve project goals more efficiently. As the function of FPGA design tends to be complex and the scale becomes larger, the traditional debugging methods have some defects, such as poor perspective, unable to debug internal signals, slow debugging speed and so on, which can not meet the needs of the present stage, so it is urgent for FPGA developers to find a more efficient and adaptive debugging method.

EXOSTIV waveform debugger. It provides similar simulator visibility-200000 times higher than JTAG-based tools-for standard and custom FPGA boards with fast debug turnaround times.

EXOSTIV debug system components

Compare with traditional debugging methods

Main functional features

EXOSTIV waveform debugger can improve FPGA visibility by 200000 times. It uses multiple Gbit transceiver interfaces of FPGA chip to store recorded waveform data to devices outside FPGA, and its data collection does not occupy the resources of FPGA chip itself. At present, the waveform debugger can store the maximum debugging data of 8GB, support continuous recording of 32768 internal signals at the same time, and hardware accelerated testing tools can read and display large-scale digital and analog waveform data.

Xilinx version supports Zynq, 7 series and UltraScale (+) series

Intel version supports 10 series Cyclone V and Stratix V series

Need to use FPGA manufacturer software to synthesize IP

Highest 4x12.5 Gbps MGT connection

MYRIAD Waveform Viewer (TB level)

EXOSTIV debugging system

EXOSTIV Probe and connection line

working principle

Establish a link between the IP core and the debugger: set the chip type

Link method (HDMI or SFP), etc.

Set up the capture unit: configure the signal to be collected and its trigger

Conditions

Generate an IP core and inject it into the design: according to the configuration in the first two steps

Generate the IP core, and the debugger will inject the IP core into the design, according to the IP

The setting in the core begins to capture the signal

Configure the conditions and run: after the IP core generation is completed, the user still

Some modifications can be made to the capture unit, such as triggering

Condition, trigger position, etc.

Read the image and debug: the collected data passes through the high-speed serial port.

Stored in Probe, you can view the coexistence in the waveform debugging interface.

Store waveforms.

EXOSTIV working schematic diagram

Waveform debugging interface

Support connection mode

SFP/SFP+/QSFP/QSP+ interface

HDMI interface, or Micro-HDMI connector

Connect to FMC, use FMC to HDMI, FMC to

SFP/QSFP module adapter.

Support chips and platforms

We can see that many emerging industries, such as cloud computing, 5G communications, artificial intelligence (AI), machine learning, autopilot and other application scenarios need strong computing power to support, so FPGA is widely used in various fields, while the design tends to be complex, they also take up more logic resources, semaphores also show an exponential increase, the emergence of EXOSTIV provides a more powerful signal visualization ability. There is no doubt that it facilitates the debugging work of electronic engineers and delivers the FPGA design faster.

After reading the above, have you mastered the method of EXOSTIV waveform debugger to provide innovative debugging case analysis for FPGA? If you want to learn more skills or want to know more about it, you are welcome to follow the industry information channel, thank you for reading!

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