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How to carry out physical aware synthesis analysis, in view of this problem, this article introduces the corresponding analysis and solutions in detail, hoping to help more partners who want to solve this problem to find a more simple and feasible method.

Everything is the need of development, process renewal has brought great challenges to the entire semiconductor industry, from production equipment to EDA to chip design and implementation are all out of breath in the light of Ze technology. The following figure is from DAC15 Andrew B. Kahng on synthesis's slide, which visually shows the factors introduced by process progress from 65nm to 16/14nm, physical implementation, especially STA.

In the part of chip design and implementation, Prunr engineers will feel the challenges brought by the process more directly, and there are new points and methodology updates with STA and DFT, but most of them are tightly wrapped by EDA tools. In terms of synthesis, the biggest update compared to traditional synthesis is physical aware synthesis, but for most integrated engineers, this seems to be a natural thing, you use it or not. Flow is right there, no yelling or yelling. Donkey today on their own superficial understanding, on this point to make a simple argument.

Why do you want to physical aware synthesis?

The most fundamental goal is to reduce the number of iterations at the front and back end. The root cause of the large number of iterations at the front and back end is the correlation difference, while correlation needs to be viewed from two aspects: timing and congestion:

Timing

The object of comprehensive optimization is timing path, while timing path delay = net delay + cell delay,90nm was dominated by cell delay before, but the proportion of entering 65nm net delay is increasing day by day, and after entering 40, it is almost equal to cell delay, so physical aware synthesis is well known by silicon farmers since 40, because physical aware synthesis can see a more accurate net delay in the optimization process.

Why can't logical synthesis accurately calculate net delay?

This takes a look back at how the traditional synthesis estimates net delay. The traditional synthesis is commonly known as logic synthesis, which estimates net delay according to WLM. WLM (wire load model) is provided by foundry. WLM usually includes area coefficient, capacitance coefficient and resistance coefficient per unit length, as well as a table for estimating the length of net. The index of the table is fanout, which, to put it bluntly, simulates the length of net as a function of fanout.

Look at the following figure: according to WLM, all net lengths from blue to red are the same, and so is net delay, but in fact, net walks in a variety of positions, it is impossible to be the same at all, and the disadvantages are obvious. Another defect is that the unit capacitance resistance of WLM is a constant value, which can not simulate the difference of different layer RC values. After entering 16nm, the net delay of layer aware must be considered. After entering 7nm, besides the influence of VIA on net delay, why should VIA be considered? Because the proportion of VIA delay can not be ignored.

In 40 or even 28, some people are still using the traditional way to do synthesis, which is simple and rough to add 30% or more clock cycle overappointment, which is possible to cover net delay, but it is too much. According to statistics, more than 80% of the wires in a chip are short lines. For less than 20% of the cover lines, the price paid is larger area and more power consumption. Of course, if you don't care, it doesn't matter. After all, willfulness is one of the characteristics of your tuhao!

How does Physical aware synthesis calculate net delay more accurately?

To accurately calculate the net delay, you must know the walking posture of the net, and to know the walking posture of the net, you must know: where does it come from? Where are you going? This requires knowing the location of the cell. After the location of the cell is determined, the integrated tool will do global winding and estimate the net delay according to the results of the global winding. The location of cell is determined by placement, so today's integrated tools integrate the placement engine, which is the key to doing physical aware synthesis. There are probably two ways to do place:

After the optimization and mapping, do place, the operation object is std cell.

Place is done at the beginning of optimization after elaborate, that is, the so-called early physical. In the early stage, palce,mapping is done for module and then place is done for std cell.

The following picture is a random picture on Google, just to show what module place is. From the Layout, each color corresponds to a module, corresponding to the hierarchical in RTL, so the QA of module place will have a great impact on PPA. The integrated tools are basically based on the three major steps of translation + optimization + mapping, and the selection of all structures and most of the optimized actions are completed in optimization. If you can know the location information of module in optimization, optimization will be more targeted and will be able to "strike accurately", so Early physical is very necessary. The trend we are seeing now is to bring more physical information to the front end, and the sooner we consider the physical information, the better.

Conclusion: according to the real physical information, physial aware synthesis can accurately estimate net delay, and it is layer and VIA aware by using the same place engine and global route engine as Prunr. Usually, physical aware synthesis only needs to pass about 5% or 10% of the clock cycle, which can be used for the influence of conver legalization and detail route.

Congestion

Similarly, due to the progress of the process, the improvement of integration, and the sharp increase in the number of lines to go per unit area, congestion has become a problem that should be paid attention to from the RTL design, otherwise the winding will not get through, and everything done in front of it will become useless. Obviously, congestion can not be considered in logical synthesis, and physical aware synthesis is necessary to optimize congestion in the synthesis stage.

In fact, no matter whether PPA or congestion dominates the decision-making power, architecture and algorithm design is the "powerful" that really determines everything. That's why it is said that implementation is a soulless type of work, as long as it goes down according to the rules set by the design / EDA/foundry, and the only thing to avoid is to "play".

There are only two basic things that congestion synthesis tools can do: choose structures and push cell. As for the optional structure, a bad example is to split a large MUX into multi-level MUX to solve the congestion. Pushing cell depends entirely on the EDA tool. If you don't know how to do it, find the AE variable or option to have the tool push the cell of the congestion critical area when doing place. In addition, there is one thing that can be artificially intervened to disable or make tools use less complex cell with small size, such as x1's AOI/OAI.

In particular, after 16, the impact of layer is particularly great, so the integrated DEF must have a special net part, that is, your power plan, so that the tool can clearly know which layer winding resources have been occupied.

The answers to the questions on how to analyze physical aware synthesis are shared here. I hope the above content can be of some help to you. If you still have a lot of doubts to be solved, you can follow the industry information channel to learn more about it.

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