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This article mainly explains "what are AXI BRAM Controller and BMG". Friends who are interested may wish to have a look. The method introduced in this paper is simple, fast and practical. Let's let the editor take you to learn what AXI BRAM Controller and BMG are.

AXI BRAM Controller

The block RAM is used as the slave core of the AXI Endpoint in the AXI interconnect and communicates with the local block RAM as the system master device.

AW: write address channel

AR: degree address channel

W: write data channel

B: write response channel

R: read data channel

Write operation mode:

1. All write operations are initialized by the write address channel (AW) of the AXI bus, which transmits write protocols and address information.

two。 Write data channel (W) to transmit all three write or burst write operations

3. The write response channel (B) is used to process the feedback of the write operation.

Read operation mode:

1. When the AXI master device requests a read transmission, the read address channel (AR) transmits all addresses and can control information.

two。 During the read operation, the AXI slave device BRAM controls the IP response read address channel (AR).

3. When the AXI master device can read the data, read the data channel (R) to get the data and operation mode.

Block memory generator (BMG)

BMG core is an advanced storage constructor with Native and AXI4 interfaces. Port An of BRAM is designated as the write port and port B of BRAM is designated as the read port.

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