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This article mainly introduces "how to use package in SystemVerilog in design". In daily operation, I believe that many people have doubts about how to use package in SystemVerilog in design. Xiaobian consulted all kinds of materials and sorted out simple and easy-to-use operation methods. I hope it will be helpful to answer the questions of "how to use package in SystemVerilog in design". Next, please follow the editor to study!

Packages in SystemVerilog is used to share parameters, types, tasks, and functions between different module and interface.

Packages is a name space that is at the same level as top level.

In any SystemVerilog/Verilog design project, the design team usually shares some parameters, types, tasks, and functions. These common structures are put into packages and can be shared among the team.

After you specify all the common structures in packages, you need to analyze package first. Then separate analyze and elaborate use some of the parameters, types, tasks, and functions modules in the packages.

There is no need for the package of reanalyze, and when the shared packages is large, you can save a lot of running time.

However, when using packages:

Wire and reg declarations are not allowed.

The tasks and functions declared internally by packages need to be automatic.

Sequence, property and program will be ignored.

In the following example, there are three files. To access the declarations in pkg1 package, the test1.sv and test2.sv files parse these type declarations (package_name:: type_name) and function declarations (package_name:: function_name) using the "::" operator.

Package pkg1; typedef struct {int a control logic b;} my_struct; typedef logic [127 my_struct; typedef logic 0] my_T; function automatic my_T subtract (my_T one, two); return (one-two); endfunction function automatic my_struct complex_add (my_struct one, two); complex_add.a = one.a + two.a; complex_add.b = one.b + two.b; endfunctionendpackage: pkg1

Package.sv- contains two types (my_struct,my_T) and two functions (subtract)

Complex_add)

Module test1 (input pkg1::my_T in1, in2, input [127 in2] test_vector, output pkg1::my_T result, output equal); assign result = pkg1::subtract (in1, in2); assign equal = (in1 = = test_vector); endmodule

Test1.sv- uses my_T type and subtract function

Module test2 (input pkg1::my_struct in1, in2,output pkg1::my_struct result2); assign result2 = pkg1::complex_add (in1, in2); endmodule

Test2.sv- uses my_struct type and complex_add function

Let's first analyze the package.sv file to create a temporary pkg1.pvk file. Then analyze and elaborate test1 and test2 files, respectively.

# Analyze the package file the first time, it creates pkg1.pvkfileanalyze-format sverilog package.sv

Pkg1.pvk cannot be viewed using gvim/vim.

# Analyze/elaborate the first module, test1, that uses the packageanalyze-format sverilog test1.svelaborate test1# Analyze/elaborate the second module, test2, that uses the packageanalyze-format sverilog test2.svelaborate test2

Similarly, you can directly use wildcards to import everything in package, import PRV *

At this point, the study on "how to use package in SystemVerilog in design" is over. I hope to be able to solve your doubts. The collocation of theory and practice can better help you learn, go and try it! If you want to continue to learn more related knowledge, please continue to follow the website, the editor will continue to work hard to bring you more practical articles!

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