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This article shows you how to carry out the manual simulation of ModelSim, the content is concise and easy to understand, it can definitely brighten your eyes. I hope you can get something through the detailed introduction of this article.

0.1 New simulation project

Before we start the hands-on simulation, we first need to create a folder to place our ModelSim simulation project files, where we create a manual_modelsim folder in the simulation folder under the Quartus project directory we created earlier. After the manual_modelsim folder is created, we also need to add the written Verilog simulation file and Testbench simulation file to our manual_modelsim folder, and here we copy the Verilog_First.v file and Verilog_First.vt file used for automatic simulation to the manual_modelsim folder. (the Verilog_First.v file is in our Quartus II project directory, and the Verilog_First.vt file is in the modelsim folder under the simulation folder under our Quartus II project directory. After completing the above preparations, we can open the ModelSim-Altera 10.1d (Quartus II 13.1) software. What we need to note here is that the ModelSim software version we opened is the free version of ModelSim-Altera Starter Edition. After opening the software, we find the [File] → [New] → [Project] menu in the menu bar of the ModelSim software interface and click to open it. The pop-up dialog box is shown in the figure.

We can see from the dialog box, Project Name (project name) is used to set our project name, here we name it as Verilog_First, here naming method, we suggest that you had better name according to our simulation file, for a long time, when we can not remember what the simulation project is used for simulation, we see this project name, we can know what it is used to do. Project Location (project path), you can set the folder where the project is saved, and users can save the project to different locations according to their needs. Here we set the path in the E:/A4_Plus_Verilog/Verilog_First/simulation/manual_modelsim folder. The following two sections are used to set the simulation library name and path, here we can use the default. After setting the project name and project location, we click the [OK] button and pop up as shown in the figure. We can see from the selection window in the figure that it has four operations: Create New File (create new file), Add Existing File (add existing file), Create Simulation (create simulation) and Create New Folder (create new folder). Here we select Add Existing File (add existing files), as shown in the figure

On this page, we can see that we have added two of our pre-prepared documents, Verilog_First.v and Verilog_First.vt, to our ModelSim simulation project. After adding it, we click the [OK] button, and then we close the [Add items to the Project] dialog box, as shown in the figure

0.2 compile the simulation file

After adding the file, we then need to compile our simulation file. There are two kinds of compilers: Compile Selected (selected for compilation) and Compile All (compile all). To compile the selected function, you need to select one or more files, execute this command to complete the compilation of the selected files; compile all the functions do not need to select the file, the command is to compile all the files in the project in the compilation order. You can find these two commands in the menu bar [Compile], in the shortcut toolbar or in the right-click pop-up menu in the workspace. Next, we click Compile All (compile all), and the Status column may have three different states after compiling the file as shown in the figure. In addition to the pass status shown in "√" above, there are two unwanted states in the design: compilation errors and compilation passes with warnings. A compilation error means that Modelsim cannot complete the compilation of the file. Usually this is because the compiled file contains obvious syntax errors, which is because Modelsim will recognize these syntax errors and prompt the user, who can modify them according to the prompt message of Modelsim. When compiling errors, the red "x" is displayed in the Status column. A compilation pass with warnings is a special state that indicates that the compiled file has no obvious syntax errors, but may contain some factors that affect the final output. This kind of state will rarely appear in practical use, and it will also display "√" in the Status column, but there will be a yellow triangle symbol after the check mark. This kind of information generally will not have an obvious impact on functional simulation, but it may cause inestimable errors in subsequent synthesis and timing simulation, so readers are recommended to modify the code according to warning messages when this state occurs. Ensure the security of subsequent use.

After configuring the simulation environment, we began to configure the simulation environment. We found the [Simulate] → [Start Simulation...] menu in the ModelSim menu bar and clicked it. From the configuration simulation function page, we can see that there are six tags in the page, which are: Design, VHDL, Verilog, Libraries, SDF and Others. For these six tags, we use the most is Design, Libraries and SDF, these three tags, let's briefly introduce these three tags, the rest of the tags we generally do not need, we will not introduce here. First of all, introduce the Design tag, the middle part of the tag is the full library contained in Modelsim, you can expand to see the design units contained in the library, these libraries and units are for simulation to provide choice, users can choose the design unit that needs to be simulated to start the simulation, the name of the selected simulation unit will appear in the Design Unit (s) location below. Modelsim supports simulations of multiple files at the same time. You can use Ctrl and Shift keys to select multiple files, and all selected file names will appear in the Design Unit (s) area. On the right side of the Design Unit (s) area is the Resolution option, where you can select the timescale for the simulation. The concept of timescale is similar to the meter of length measurement. When Modelsim performs a simulation, there is a minimum time unit that can be specified by the user. For example, if the smallest unit is 10ns, the simulation is carried out in 10ns units when the simulator works, and the signal changes that occur in 10ns units are not considered or displayed. When the test document has a sentence similar to # 1 axi1roomb1;, Modelsim will not consider the delay in the sentence. This option is generally set to the default state, which will simulate according to the minimum timescale specified in the simulator, or press 1ns if it is not specified in the design file. The bottom area is the Optimization area, which can activate the optimization at the beginning of the simulation. Since we are a free version, many features are limited, so we can see that we cannot use it here. The second introduced tag is the Libraries tag, as shown in the figure on this page, we can set up a search base, we can specify a library to search for instantiated VHDL design units. The functions of Search Libraries and Search Libraries First are basically the same, except that the libraries specified in Search Libraries First are specified to be searched before the user libraries. The third tag is SDF, which is an acronym for Standard Delay Format (Standard delay format) as shown in the figure. It contains all kinds of delay information and is an important file for timing simulation. The SDF Files area is used to add SDF files, select Add to add, select Modify to modify, and select Delete to delete the added files. SDF Options sets the warning and error information for the SDF file. The first Disable SDF warning is to disable SDF warnings, and the second Reduce SDF errors to warnings is to program warning messages for all SDF error messages. Multi-Source delay can control the drive of multiple targets to the same port. If multiple control signals control the same port or interconnection at the same time, and the delay value of each signal is different, you can uniformly delay in this option. There are three options available in the drop-down menu: latest, min, and max. Max selects the value of the maximum delay of all signals as the unified value, min selects the value of the minimum delay of all signals as the unified value, and latest chooses the final delay as the unified value. At this point, we have finished introducing these three tags. Next, we select the Verilog_First_vlg_tst module in the work library in the Design tag page, and then click [OK] to start the functional simulation. We can use the default configuration in the rest of the tag page. 0.4 start functional simulation before simulation, there are usually only two tags Project and Library in the Workspace area. After starting the simulation, sim tags, Files tags, and Memory List tags are generally added in the Workspace area. In addition to the Workspace area, a new Object window will also appear in the MDI window. Select a design unit in the sim tab in the Workspace area, and the input / output port contained in the unit will appear in the Object window. As shown in the figure below, we select the signal we need to simulate in the Object window, then right-click, find [Add Wave] in the pop-up menu bar and click, we will find Our signal is added to the Wave window. At this time, we can press the shortcut key F9, or we can find the [Run] button in the menu bar of ModelSim. Click run and the waveform we want will appear. What we need to note here is that the default run time is 100ps, and we can modify it in the menu bar, or we can directly enter the command run 100ns in the console and run 100ns directly, as shown in the figure.

At this point, we have completed the manual functional simulation, and the following work is to analyze our simulated waveforms, because this part of the content is exactly the same as what we are talking about in the automatic simulation. so we won't repeat it any further. The above content is how to carry on the manual simulation of ModelSim. Have you learned the knowledge or skills? If you want to learn more skills or enrich your knowledge reserve, you are welcome to follow the industry information channel.

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