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How to use TI DSP TMS320C6678 processor for TI-IPC multi-core communication, many novices are not very clear about this, in order to help you solve this problem, the following editor will explain in detail for you, people with this need can come to learn, I hope you can gain something.

How to use TMS320C6678 processor for TI-IPC multi-core communication case

Based on Chuanglong Technology TL6678-EasyEVM evaluation board for demonstration.

Figure 1TL6678-EasyEVM evaluation board

TL6678-EasyEVM is a high-end multi-core DSP evaluation board based on TI KeyStone architecture C6000 series TMS320C6678 8-core C66x fixed-point / floating-point high-performance processor, which is composed of core board and backplane. The core board has been verified by professional PCB Layout and high and low temperature tests, it is stable and reliable, and can meet a variety of industrial application environments.

The evaluation board is rich in interface resources, which leads to two-way gigabit network ports, SRIO, PCIe and other high-speed communication interfaces, which is convenient for users to quickly carry out product scheme evaluation and technical pre-research.

The development cases mainly include:

(1) bare metal development case

(2) RTOS (SYS/BIOS) development case

(3) Multi-core development cases of IPC and OpenMP

(4) Development cases of SRIO, PCIe and double Gigabit network ports

(5) Image processing development case

(6) the development case of DSP algorithm

(7) the development case of serial port and network remote upgrade.

Case source code, product materials (user manual, core board hardware materials, product specifications) can be obtained by site.tronlong.com/pfdownload.

1.1 introduction to TI-IPC

TI-IPC (Inter-Processor Communication) is a component that provides API independent of processor hardware, which can be used for multi-core processor inter-core communication, same processor inter-process communication and inter-device communication. API supports messaging, streaming, and link lists, which are compatible in both uniprocessor and multiprocessor configurations.

TI-IPC is designed to be used on processors running SYS/BIOS applications, typically DSP processors (such as TMS320C6678, TMS320C6657), but in some cases it may also be ARM processors.

Figure 2

Common communication modules for IPC are as follows:

Table 1

Ipc

Provides the Ipc_start () function and allows you to configure the startup order

MessageQ

Variable size messaging module

Notify

A module that realizes lightweight data transmission in an interrupt way

ListMp

Used to achieve mutually exclusive access to the list of links

GateMp

Used to realize mutually exclusive access to shared resources

HeapBufMp

Fixed size shared memory heap

HeapMenMp

Variable size shared memory heap

SharedRegion

Used to maintain shared memory areas

List

Used to create a two-way link list

MultiProc

Used to manage multicore processor core ID

NameServer

For applications to retrieve based on local names and to store variable values

Figure 4

MessageQ sends and receives messages through message queuing. Reader is a thread that reads messages from a message queue, and writer is a thread that writes messages to a message queue. Each message queue has one reader, but can have multiple writer.

N reader: call MessageQ_create (), MessageQ_get (), MessageQ_free (), and MessageQ_delete ().

N writer: call MessageQ_open (), MessageQ_alloc (), MessageQ_put (), and MessageQ_close ().

The common workflows of MessageQ are shown below.

Figure 6

Figure 8

(3) it can only be used based on Shared Memroy.

Figure 10

1.3 physical transmission mode

The data transmission of TI-IPC needs to be combined with specific physical hardware and underlying drivers in order to realize the communication between two threads on the same device or across devices. The three commonly used physical transmission methods include Shared Memory, Multicore Navigator and SRIO, as described below.

Table 2

Transmission mode

Advantages

Shortcoming

Shared Memory

Easy to use and high speed

Can only be used for IPC communication on a single device, and may compete with other tasks using Shared Memory

Multicore Navigator

The highest speed and the least CPU cycle consumption

Only available for IPC communication on a single device

SRIO

Can be used for cross-device IPC communication

The lowest rate

The following figure shows the API call process using Multicore Navigator and SRIO. Users only need to pay attention to some operations of MessageQ, and other modules are automatically called by the system.

Figure 11

Figure 12

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