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It is believed that many inexperienced people are at a loss about how to prevent reg and wire signals from being optimized when using logic analyzers. Therefore, this paper summarizes the causes and solutions of the problems. Through this article, I hope you can solve this problem.

What we bring today is "how to prevent reg and wire signals from being optimized when using logic analyzers", needless to say, on stock.

With the increasing complexity of FPGA design, the logic analysis function of the chip becomes more and more important. The logic analyzer at the hardware level is very expensive and the operation is complicated. At present, the two major suppliers of FPGA chips provide software-level logic analyzers for their FPGA chips, which can help us to analyze the internal logic of the chip online. And the operation is simple and convenient, but often for some reasons, some signals will be optimized when they are integrated, which may lead to our design failure. Of course, the signal can not be found when adding the observation signal to the logic analyzer. Thus it brings some inconvenience to the work of designers and debuggers.

The following is a summary based on the logic analyzer ChipScope of Xilinx and the SignalTap of Altera.

First, before using Xilinx's ChipScope to use ChipScope to observe the signals inside the chip, add the signals that need to be observed to the ChipScope signal observation list. In other words, we must be able to find the corresponding signal in the comprehensive Netlist file. If you are using XST synthesis, it is best to keep the internal structure of the chip so that you can find the signals you need to observe in the corresponding sub-modules. By default, Chipscope can only observe signals of type reg. However, you can also observe the wiretype signal by setting the property. The attributes that need to be added are also different when using different comprehensive tools.

1. Use XST synthesis.

The main results are as follows: (1) for the regal signal, if it is optimized by ISE, it is generally possible to perform "and", "OR" and other operations between this signal and other unoptimized signals, so as to achieve the purpose of observing the signal.

(2) for wire models, for later versions of ISE12.3, XST synthesis, take Spartan3 as an example, you can use (* KEEP= "TRUE") wire [15:0] CPLD_ AD; so that you can find wire type CPLD_ AD signals in the search signal for observation.

2. Using Synplify Pro synthesis Synplify Pro has different comprehensive properties for wire and reg signals.

(1) for wire signals, use / synthesis syn_keep=1 / composite attributes, such as the following statement: wire [7:0] data_in / synthesis syn_keep=1 * /

(2) for regal signals, use / * synthesis preserve = 1 / composite attributes, such as the following statement: reg [7:0] data_in / synthesis preserve = 1 * /

Second, use SignalTap of Altera Company

1. Use the synthesizer of Altera to synthesize the synthesizer of Altera. In order to prevent some signal synthesizer from being optimized, it also has its own set of comprehensive constraint attributes.

(1) for regressive signals, in order to prevent the Altera from being optimized by its own synthesizer, the noprune attribute can be added. This prevents some register signals from being optimized. You can also use / synthesis noprune/ to synthesize properties. `include "define.v"

Module SignalTap_test (Clk, Rst, Cnt) / synthesis noprune/

Input wire Clk; input wire Rst; output reg [7:0] Cnt; always@ (posedge Clk or posedge Rst) begin if (Rst = = 1'b1) Cnt

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