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This article introduces the relevant knowledge of "What is the principle of Retiming in FPGA". In the operation process of actual cases, many people will encounter such difficulties. Next, let Xiaobian lead you to learn how to deal with these situations! I hope you can read carefully and learn something!

1 Definition of Retirement

Retiming is a timing optimization technique used to improve design performance across combinational logic registers without affecting the input/output behavior of the circuit.

2 Purpose of Retirement

Retiming is to readjust the timing, for example, the circuit encounters complex combinational logic, the delay is too large, the circuit timing is not satisfied, at this time pipeline technology is adopted, registers are inserted into the combinational logic, and the operation is carried out.

3 Principles of Retirement

We know that any digital circuit can be equivalent to combinational logic plus D-flip-flops, and the combinational logic path between the two D-flip-flops determines the operating frequency of the system and determines the performance of the chip. Therefore, in order to improve the operating frequency of the chip, the pipeline technology is used to insert registers in the combinational logic.

The position of the inserted register needs to be carefully selected, and the number of registers consumed by the beat of different position data is also different. For example, you consume 25bit registers at position a and 20bit registers at position b.

The position of the preceding inserted registers is such that comb1 has a delay of 30ns and comb2 has a delay of 10ns, and the highest operating frequency of the system is determined by the longest path. That is to say, the period of the highest operating frequency of your system is not less than 30ns, and the front is the insertion pipeline. At this time, we do not change the timing, and use the retiming technology to make the delay between each combination logic equal. 4 Vivado and Retiming

There are two ways to implement automatic retiming (global timer) in Vivado synthesis operations. Global retiming is for the entire design, optimizing register design in large combinational logic structures based on timing requirements at design time.

This approach involves analyzing all logic in the design and optimizing registers for worst-case paths to make the overall design more responsive. To achieve this, the design must specify precise time limits in the.xdc file. Global retiming is enabled with the-retiming command under synth_design or Vivado GUI synthesis settings, and can be used with the BLOCK_SYNTH attribute in composition for specific modules in a design.

Partial retiming refers to the retiming logic that the user explicitly tells the tool to perform when using the retiming_forward, retiming_backward RTL attributes. The partial retiming operation should be performed with care because it is not timer driven, but rather the tool will perform exactly as the user requests. As shown below (UG901)

If it is retiming_forward, just modify (*retiming_backward = 1 *) reg my_sig; to (*retiming_forward = 1 *) reg my_sig;

Note that the Retiming operation cannot be performed under the following circumstances:

Register timing exception (multi-loop path, wrong path, maximum delay path)

Register type attribute cannot be changed (DONT_TOUCH, MARK_DEBUG)

Registers with different control stages

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