Shulou(Shulou.com)05/31 Report--

This article mainly introduces "how to write Linux Makefile". In daily operation, I believe many people have doubts about how to write Linux Makefile. The editor consulted all kinds of materials and sorted out simple and easy-to-use operation methods. I hope it will be helpful to answer the doubts about "how to write Linux Makefile". Next, please follow the editor to study!

Suppose we have a program that consists of five files with the following source code:

/ * main.c*/

# include "mytool1.h"

# include "mytool2.h"

Int main ()

{

Mytool1_print ("hello mytool1!")

Mytool2_print ("hello mytool2!")

Return 0

}

/ * mytool1.c*/

# include "mytool1.h"

# include

Void mytool1_print (char * print_str)

{

Printf ("This is mytool1 print:% s", print_str)

}

/ * mytool1.h*/

# ifndef _ MYTOOL_1_H

# define _ MYTOOL_1_H

Void mytool1_print (char * print_str)

# endif

/ * mytool2.c*/

# include "mytool2.h"

# include

Void mytool2_print (char * print_str)

{

Printf ("This is mytool2 print:% s", print_str)

}

/ * mytool2.h*/

# ifndef _ MYTOOL_2_H

# define _ MYTOOL_2_H

Void mytool2_print (char * print_str)

# endif

First, take a look at make and linux Makefile. GNU make is a project manager that can manage more files. The make version of RedHat 9.0 that I use is GNU Make version 3.79.1. The advantage of using make is that it can be compiled automatically. If there is a project made up of hundreds of files and one or more files have been modified, make can automatically recognize the updated file code and complete the compilation work without typing a lengthy command line. When make executes, it automatically looks for the Makefile (makefile) file, and then performs the compilation work. So we need to write Makefile files, which can improve the efficiency of the actual project.

A linux Makefile usually contains the following:

1. A target that needs to be created by the make tool, usually an object file or an executable file.

2. The file (dependency_file) on which the target body to be created depends.

3. The command (command) to be run when creating each target body.

The format is as follows:

Target:dependency_files

Command

Target: the goal of the rule. It is usually the file name that needs to be generated in the middle of the program or * *. It can be a .o file or the file name of an executable program. In addition, the target can also be the name of an action performed by a make, such as the target "clean", which is called a "pseudo target". Dependency_files: dependence on rules. Generate a list of file names required by the rule target. Usually a target depends on one or more files.

Command: the command line for the rule. Is all the actions performed by a make program (any shell command or a program that can be executed under shell) A rule can have multiple command lines, each command on one line. Note: each command line must start with the [Tab] character, which tells make that this line is a command line. Make completes the corresponding action according to the command. This is also an easy and hidden mistake in writing Makefile. The command is the action description that rebuilds the target after the dependency file of any target changes. A target can have no dependencies and only actions (specified commands). For example, the target "clean" in Makefile has no dependencies, only commands. The command it specifies is used to delete intermediate files generated by the make process (cleanup work).

In Makefile, a "rule" is an object file that describes when and how to reconstruct a rule. Usually, the rule includes the dependency of the target (the dependency file of the target) and the command to rebuild the target. Make executes the command to rebuild the target to create or rebuild the target of the rule (this target file can also be a dependent file in the previous rule that triggered the rule). The rules contain the relationship between the goal and the dependency and the commands required to update the goal.

The Makefile can contain parts other than rules. The simplest Makefile may contain only a description of the rules. Rules may seem very complex in some Makefile, but no matter how complex the rules are written, they conform to the basic format of the rules.

Then you can write * Makefile.

Main:main.o mytool1.o mytool2.o

Gcc-o main main.o mytool1.o mytool2.o

Main.o:main.c mytool1.h mytool2.h

Gcc-c main.c

Mytool1.o:mytool1.c mytool1.h

Gcc-c mytool1.c

Mytool2.o:mytool2.c mytool2.h

Gcc-c mytool2.c

Clean:

Rm-f * .o main

Enter make at the shell prompt to perform the display:

Gcc-c main.c

Gcc-c mytool1.c

Gcc-c mytool2.c

Gcc-o main main.o mytool1.o mytool2.o

The implementation results are as follows:

[armlinux@lqm makefile-easy] $. / main

This is mytool1 print: hello mytool1!

This is mytool2 print: hello mytool2!

This is only the most rudimentary Makefile, now let's improve on this Makefile.

Improvement 1: using variables

Generally speaking, when writing Makefile, the format of variable references in each part is as follows:

1. Make variable (Mak1. References to make variables (defined in Makefile or make's environment variables) use the format "$(VAR)", regardless of whether "VAR" is a single-character variable name or a multi-character variable name.

two。 The shell variable, which appears on the regular command line (usually a temporary variable during command execution, is not a Makefile variable, but a shell variable) refers to the "$tmp" format that uses shell.

3. Make variables that appear on the command line are also referenced using the "$(CMDVAR)" format.

OBJ=main.o mytool1.o mytool2.o

Make:$ (OBJ)

Gcc-o main $(OBJ)

Main.o:main.c mytool1.h mytool2.h

Gcc-c main.c

Mytool1.o:mytool1.c mytool1.h

Gcc-c mytool1.c

Mytool2.o:mytool2.c mytool2.h

Gcc-c mytool2.c

Clean:

Rm-f main $(OBJ)

Improvement 2: using automatic derivation

Let make automatically deduce, as long as make sees a .o file, it will automatically add the corresponding .c file to the dependent file, and gcc-C. c will also be deduced, so Makefile is simplified.

CC = gcc

OBJ = main.o mytool1.o mytool2.o

Make: $(OBJ)

$(CC)-o main $(OBJ)

Main.o: mytool1.h mytool2.h

Mytool1.o: mytool1.h

Mytool2.o: mytool2.h

.PHONY: clean

Clean:

Rm-f main $(OBJ)

Improvement 3: the application of automatic variables ($^ $< $@)

Makefile has three very useful variables, which are $@, $^, and $

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.