Shulou(Shulou.com)06/01 Report--

This article introduces the relevant knowledge of "how to use controller". In the operation of actual cases, many people will encounter such a dilemma, so let the editor lead you to learn how to deal with these situations. I hope you can read it carefully and be able to achieve something!

Basics:

First, let's take a look at the lcd controller composition block diagram of 2440:

REGBANK: the register group of the LCD controller, containing 17 registers and a palette of 256x16

LCDCDMA: a dedicated DMA channel of the LCD controller that automatically acquires image data from the system bus and does not require the participation of cpu core when displaying the image

TIMEGEN / LPC3600: generate control timing, such as VSYNC, HSYNC, VCLK, VDEN, and these signals are closely related to the configuration of LCDCON1/2/3/4 in REGBANK, and different control signals are generated through different configurations. Then pass it from VIDEO MUX to LCD screen (LPC3600 is for STN screen only)

VIDPRCS: receive the data from LCDCDMA and convert it to the appropriate data format, such as 4bit single scan / 8ibt single scan / 4bit double scan, and then display by VD [23:0]

Second, let's analyze the timing of lcd controller:

VSYNC/VFRAME/STV: vertical synchronization signal (TFT) / frame synchronization signal (STN) / SEC TFT signal HSYNC/VLINE/CPV: horizontal synchronization signal (TFT) / line synchronization pulse signal (STN) / SEC TFT signal VCLK/LCD_HCLK: pixel clock signal (TFT/STN) / SEC TFT signal VD [23:0]: LCD pixel data output port (TFT/STN/SEC TFT) VDEN/VM/TP: Data enable signal (TFT) / LCD drive AC bias signal (STN) / SEC TFT signal LEND/STH: line end signal (TFT) / SEC TFT signal LCD_LPCOE: SEC TFT OE signal LCD_LPCREV: SEC TFT REV signal LCD_LPCREVB: SEC TFT REVB signal

All monitors display images from top to bottom and from left to right. What does this mean? To put it this way, an image can be thought of as a rectangle, consisting of many neatly arranged rows of dots called pixels. So the principle of this picture on LCD is:

A: the display pointer starts from the first point in the first row of the upper left corner of the rectangle, and a dot is displayed on the LCD, which is represented as VCLK on the timing chart above. We call it the pixel clock signal B: when the display pointer is displayed all the way to the right side of the rectangle, the action of this line is called 1 LineC in the timing chart above: then the display pointer goes back to the left side of the rectangle, starting with the second line. Note that it takes some time for the display pointer to go from the right side of the first row to the left of the second row, which we call row toggle D: and so on, the display pointer is displayed in such a line to the lower right corner of the rectangle before a picture is displayed. The display of lines on the timing diagram is HSYNCE: however, if LCD wants to display multiple pictures, it needs to switch one by one, so each image is called a frame, which is represented as 1 Frame on the timing chart, so it can be seen from the timing diagram that 1 Line is only a row of F in 1 Frame: similarly, it takes some time to switch between frames, we call it frame switching. Then the whole process of LCD display on the timeline can be represented as VSYNC on the timing diagram.

The meanings of the clock delay parameters on the above timing diagram are as follows: (for the values of these parameters, the LCD generator will provide the corresponding data manual)

VBPD (vertical back porch): indicates the number of invalid lines after the vertical synchronization signal at the beginning of a frame image, corresponding to the upper_marginVFBD (vertical front porch) in the driver: indicates the invalid number of lines before the vertical synchronization signal after the end of a frame image, corresponding to the lower_marginVSPW (vertical sync pulse width) in the driver: indicates the width of the vertical synchronization pulse, calculated by the number of lines Vsync_lenHBPD (horizontal back porch) in the corresponding driver: indicates the number of VCLK between the start of the horizontal synchronization signal and the start of the effective data of a row; corresponding to the left_marginHFPD (horizontal front porth) in the drive; indicates the number of VCLK between the end of the effective data of one line and the beginning of the next horizontal synchronization signal; corresponds to the right_marginHSPW (horizontal sync pulse width) in the driver: indicates the width of the horizontal synchronization signal, calculated by VCLK, and corresponds to the hsync_len in the driver.

To use LCD:

Lcd_Port_Init (); / / set LCD pin Tft_Lcd_Init (MODE_TFT_16BIT_240320); / / initialize the LCD controller, where the LCD display mode is configured, such as resolution 240x320 color depth 16bit Lcd_PowerEnable (0,1); / / set LCD_PWREN valid, which is used to power on LCD Lcd_EnvidOnOff (1) / / enable LCD controller output signal ClearScr (0x0); / / clear the screen, black one setting pin GPCUP = 0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff; / / prohibit internal pull-up GPCCON = 0xaaaaaaaaaaaaaaaaaaaaaaaa / / disable internal pull-up GPDCON = 0xaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.