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How to use makefile

2025-02-24 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Development >

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This article mainly explains "how to use makefile". The content in the article is simple and clear, and it is easy to learn and understand. Please follow the editor's train of thought to study and learn how to use makefile.

Overview

What is makefile? Maybe a lot of Winodws programmers don't know this thing, because those Windows IDE have done this work for you, but I think to be a good programmer with professional, makefile still needs to understand. It's as if there are so many HTML editors, but if you want to be a professional, you still need to understand the meaning of the HTML logo. Especially in the software compilation under Unix, you have to write makefile yourself, and whether you can write makefile or not shows from one aspect whether a person has the ability to complete large-scale projects.

Because makefile is related to the compilation rules of the whole project. The source files in a project are not counted, but are placed in several directories by type, function and module. Makefile defines a series of rules to specify which files need to be compiled first, which files need to be compiled later, which files need to be recompiled, and even more complex functional operations, because makefile is like a Shell script, which can also execute operating system commands.

The advantage of makefile is "automatic compilation". Once written, only one make command is needed, and the whole project is compiled automatically, which greatly improves the efficiency of software development. Make is a command tool, is a command tool to explain the instructions in makefile, generally speaking, most IDE have this command, such as: Delphi's make,Visual C++ nmake,Linux under the GNU make. It can be seen that makefile has become a compilation method in engineering.

There are few articles about how to write makefile, which is why I want to write this article. Of course, different vendors have different make and different syntax, but their essence is on "file dependency". Here, I only talk about GNU's make. My environment is RedHat Linux 8.0 make version 3.80. After all, this make is the most widely used and the most widely used. And it is most in line with the IEEE 1003.2-1992 standard (POSIX.2).

About the compilation and linking of programs

Here, I would like to talk more about some norms and methods of program compilation. Generally speaking, whether it is C, C++, or pas, the source file should be compiled into an intermediate code file first, which is .obj file under Windows and .o file under UNIX, that is, Object File. This action is called compile. Then synthesize a large number of Object File execution files, an action called link.

When compiling, what the compiler needs is correct syntax and correct declaration of functions and variables. For the latter, you usually need to tell the compiler where the header file is located (the header file should only be declared, and the definition should be placed in the Cpassword + file), and as long as all the syntax is correct, the compiler can compile the intermediate object file. In general, each source file should correspond to an intermediate target file (O file or OBJ file).

When linking, we mainly link functions and global variables, so we can use these intermediate object files (O files or OBJ files) to link our application. The linker does not care about the source file where the function is located, despite the intermediate object file (Object File) of the function. Most of the time, because there are too many source files, there are too many intermediate target files compiled, and the intermediate target file name needs to be clearly pointed out when linking, which is very inconvenient for compilation, so we have to make a package for the intermediate target file. Under Windows, this package is called "library file" (Library File). That is, the .lib file, under UNIX, is Archive File, that is, the .a file.

To sum up, the source file first generates an intermediate target file, and then an execution file is generated from the intermediate target file. At compile time, the compiler only detects the program syntax and whether functions and variables are declared. If the function is not declared, the compiler gives a warning, but it can generate an Object File. When linking the program, the linker will look for the implementation of the function in all the Object File. If it cannot be found, it will report the link error code (Linker Error). Under VC, this kind of error is generally: Link 2001 error, which means that the linker cannot find the implementation of the function. You need to specify the Object File of the function.

OK, let's get back to the point. GNU's make has a lot of content, so let's get started.

Makefile introduction

When the make command executes, you need a Makefile file to tell make how the command needs to compile and link the program.

First, we use an example to illustrate the writing rules of Makefile. In order to give everyone a sense of interest. This example comes from GNU's make user manual. In this example, our project has eight C files and three header files. We will write a Makefile to tell the make command how to compile and link these files. Our rules are:

1) if the project has not been compiled, then all our C files will be compiled and linked.

2) if some C files of the project are modified, then we will only compile the modified C files and link to the target program.

3) if the header file of the project is changed, then we need to compile the C file that references these header files and link the target program.

As long as our Makefile is good enough, we can do all this with only one make command, which will automatically and intelligently determine which files need to be recompiled according to the current file modification, so as to compile the required files and link the target program by ourselves.

I. the rules of Makefile

Before we talk about this Makefile, let's take a cursory look at the rules of Makefile.

Target...: prerequisites... Command......

Target is an object file, which can be either an Object File or an execution file. It can also be a Label, which is described in the "pseudo-targets" section that follows.

Prerequisites is the file or target needed to generate that target.

Command is the command that make needs to execute. (any Shell command)

This is a file dependency, that is, target, one or more target files, depends on the files in prerequisites, and its generation rules are defined in command. To put it bluntly, if there is more than one file in prerequisites that is newer than the target file, the command defined by command will be executed. These are the rules of Makefile. This is the core content of Makefile.

In the final analysis, the Makefile thing is just like this, as if my document should be finished. He he. Not quite, this is the main line and core of Makefile, but it is not enough to write a Makefile, I will come to you bit by bit with my work experience. There's still a lot of content. :)

2. An example

As mentioned earlier, if a project has 3 header files and 8 C files, in order to complete the three rules mentioned above, our Makefile should look like this.

Edit: main.o kbd.o command.o display.o / insert.o search.o files.o utils.o cc-o edit main.o kbd.o command.o display.o / insert.o search.o files.o utils.o main.o: main.c defs.h cc-c main.c kbd.o: kbd.c defs.h command.h cc- C kbd.c command.o: command.c defs.h command.h cc-c command.c display.o: display.c defs.h buffer.h cc-c display.c insert.o: insert.c defs.h buffer.h cc-c insert.c search.o: search.c defs.h buffer.h cc-c search.c files.o: files.c defs.h buffer.h command. H cc-c files.c utils.o: utils.c defs.h cc-c utils.c clean: rm edit main.o kbd.o command.o display.o / insert.o search.o files.o utils.o

The backslash (/) means a newline character. This makes it easier to read Makefile. We can save this content in a file with the file "Makefile" or "makefile", and then type the command "make" directly in that directory to generate the execution file edit. If you want to delete the execution file and all intermediate target files, simply execute "make clean".

In this makefile, the target file (target) contains the execution file edit and the intermediate object file (* .o), and the dependent file (prerequisites) is the .c file and .h file after the colon. Each .o file has a set of dependent files, and these .o files are dependent files that execute the file edit. The essence of the dependency relationship is to indicate which files the target file is generated from, in other words, which files are updated.

After defining the dependency, the subsequent line defines how to generate the operating system command for the target file, which must start with a Tab key. Remember, make doesn't care how commands work, he just executes the defined commands. Make compares the modification dates of the targets file and the prerequisites file, and if the date of the prerequisites file is newer than the date of the targets file, or if the target does not exist, then make executes the commands defined later.

To make it clear here, clean is not a file, it is just an action name, a bit like lable in C language, with nothing after the colon, then make will not automatically find the file's dependencies and will not automatically execute the commands defined later. To execute subsequent commands, the name of the lable is clearly indicated after the make command. This method is very useful, we can define unused compilation or compilation-independent commands in a makefile, such as program packaging, program backup, and so on.

Thank you for your reading, the above is the content of "how to use makefile", after the study of this article, I believe you have a deeper understanding of how to use makefile, and the specific use needs to be verified in practice. Here is, the editor will push for you more related knowledge points of the article, welcome to follow!

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