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This article mainly introduces "the process introduction of ASIC physical design". In the daily operation, I believe that many people have doubts about the process introduction of ASIC physical design. The editor consulted all kinds of materials and sorted out simple and easy-to-use operation methods. I hope it will be helpful to answer the doubts of "process introduction of ASIC physical design". Next, please follow the editor to study!

Physical design is the process of transforming a circuit description (circuit description) into a physical layout (physical layout). Specify the location of the cell and the connection between them in the physical layout.

Import design: the first step in the physical design process is to import the design. RTL is converted to netlist in the synthesis phase and then read into the physical design tool in the physical design phase.

The Floorplan:Floorplan phase defines the size of the chip (die), the location of macro and io, and the definition and connection of power grid. After placing the macro, the area where the std cell and routing are placed is also defined.

Placement:Placement is the process of automatically placing std cell using physical design tools, in which in the global placement phase, the std cell is placed in the core very roughly, and in the detailed placement phase, the std cell legalize is put on the siterow to ensure that there is no overlap.

At the same time, we also need to check congestion through GRC map.

CTS (clock tree synthesis): generate a clock tree by inserting inverter and buffer during the CTS phase. Because clock signal is very important for DFF-based ASIC design, we need to balance clock skew and minimize insertion delay in the CTS phase to meet the timing (timing) and power consumption (power) requirements of the design.

Routing: before the Routing phase, only power made the actual metal wiring, and macro, std cell, clock, and io only logically defined the connection relationship (logically). In the routing phase, you need to use wire for physical connection (physical).

Signoff: after the completion of the routing phase, the physical layout of the chip has been determined. In the sign-off phase, it is necessary to ensure that the quality and performance of the chip meet the requirements before tape-out.

At this point, the study of "introduction to the process of ASIC physical design" is over. I hope to be able to solve your doubts. The collocation of theory and practice can better help you learn, go and try it! If you want to continue to learn more related knowledge, please continue to follow the website, the editor will continue to work hard to bring you more practical articles!

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