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This article mainly explains "what is the use of Verilog Basics". The content of the explanation is simple and clear, and it is easy to learn and understand. Please follow the editor's train of thought to study and learn "what is the use of Verilog Basics"?

Control Statements

If, else, repeat, while, for, case in Verilog look exactly like the C language!

But Verilog is HDL, and we need to use these keywords to describe the hardware, which means that if we are not careful with these control statements, our hardware may have problems.

If-else

The if-else statement decides which part of the code to execute based on different conditions.

/ / begin and end act like curly braces in C/C++.if (enable = = 1'b1) begin data = 10; / / Decimal assigned address = 16 roomhDEAD; / / Hexadecimal wr_enable = 1 roomb1; / / Binaryend else begin data = 32 roomb0; wr_enable = 1 roomb0; address = address + 1 × end

Like the C language, we can use any operator in Verilog conditional statements, or even nest if else statements.

But when modeling combinational logic with Verilog HDL, we need to prevent the generation of Latch.

Case

Use case statements instead of multiple nested if-else statements when you need to check for variables with multiple values.

Case (address) 0: $display ("It is 11:40PM"); 1: $display ("I am feeling sleepy"); 2: $display ("Let me skip this tutorial"); default: $display ("Need to complete"); endcase

The case statement begins with the keyword case and ends with the keyword endcase.

These case conditions and the corresponding statements you want to execute are listed in these two keywords.

Like if-else, it is recommended to add default case statements to case statements, because if the combinational logic Verilog HDL modeling, if-else and case-endcase statements do not cover all cases (there is no 'else' in If or no' default' in Case), then the synthesis tool may infer Latch.

While

If the judged condition returns true, the while statement repeats the code in the statement block. While loops are not usually used for actual hardware modeling, but they are used for test platforms (verification). Like other statement blocks, they are separated by begin and end.

While (free_time) begin$display ("Continue with webpage development"); end

The code in begin and end will always be executed as long as the free_time variable is set to true. That is, print "Continue with webpage development".

Module counter (clk,rst,enable,count); input clk,rst,enable; output [3:0] count;reg [3:0] count; always @ (posedge clk or posedge rst) if (rst) begincount

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