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ModelSim software how to understand, many novices are not very clear about this, in order to help you solve this problem, the following editor will explain for you in detail, people with this need can come to learn, I hope you can gain something.

Introduction of 1Magne ModelSim Software

Mentor's ModelSim is the best language simulator in the industry. It supports XP, Win7 and Linux systems. It is a single kernel simulator that supports VHDL and Verilog mixed simulation. It adopts directly optimized compilation technology, Tcl/Tk technology and single kernel simulation. It not only compiles and simulates the fastest speed in the industry, the compiled code is independent of the platform, but also is easy to protect the IP core. It also provides the most friendly debugging environment, with personalized graphical interface and user interface, and provides a powerful means for users to speed up debugging. It is the preferred simulation software for FPGA/ASIC design. There are several different versions of Modelsim: SE (System Edition), DE (Deluxe Edition), PE (Personal Edition), and OEM (original equipment manufacturer), of which SE is the most advanced version, while the OEM version is integrated into FPGA vendor design tools such as Actel, Atmel, Altera, Xilinx and Lattice. What we choose to use here is the OEM version provided by Altera, which is what we often call ModelSim AE (that is, ModelSim-Altera Edition). Let's give an official introduction to ModelSim AE by Altera, as shown in the figure.

As we can see in this figure, there are two versions of Modelsim Altera, one is the free version (ModelSim-Altera Starter Edition), and the other is the paid version (ModelSim-Altera Edition). Since the figure shows the difference between the paid version and the free version, we will not introduce them further. Here we will talk about the difference between the ModelSim-Altera version and the ModelSim PE/DE software. The ModelSim-Altera version only supports the Altera portal library. ModelSim-Altera version of the software includes the basic features of ModelSim PE, including behavior simulation, HDL test bench and Tcl scripts. However, the ModelSim-Altera version does not support the optional features of ModelSim PE, and the simulation performance of the ModelSimAltera version is lower than that of the ModelSim PE/DE software. After introducing the ModelSim software, let's introduce the process of using ModelSim again. Before introducing the use process of ModelSim, we need to explain the two concepts of simulation. Simulation is generally divided into pre-simulation and post-simulation: (1) pre-simulation is pure functional simulation, the purpose is to verify whether the function of the circuit meets the design requirements, and its characteristic is that the gate delay and line delay are not considered. (2) Post-simulation is time series simulation. It refers to the process that the circuit has been mapped to a specific process environment and comprehensively considers the influence of the path delay and gate delay of the circuit to verify whether the circuit meets the design concept under certain timing conditions. After talking about the two concepts of simulation, let's talk about the use of ModelSim. The use of ModelSim is mainly divided into two cases. The first is to call our ModelSim through Quartus II software for simulation, which is what we usually call automatic simulation. The second case is to open ModelSim directly for simulation without our Quaruts II software, which is what we usually call manual simulation. Whether it is automatic simulation or manual simulation, they all follow the following five steps: (1) create a new project. (2) write Verilog simulation file. (3) write Testbench simulation file. (4) start functional simulation. (5) start timing simulation. When we perform the simulation, the ModelSim software will generate the waveform according to our design file and simulation file. Finally, we observe the waveform and judge whether the designed code function is normal or not. After the completion of the pre-simulation, we need to carry out the post-simulation, and the steps of the post-simulation are roughly the same as those of the previous simulation, except that we need to add simulation libraries, Netlist and delay files and other steps. What we should note here is that for small-scale designs where timing requirements are not strict, we generally only carry out functional simulation. [note] the source code and testbench code used in this article are as follows: source code: module Verilog_First (/ / input port CLK_50M,RST_N, / / output port LED1) / /-/ /-- external port declaration / /- -input CLK_50M / / clock port, 50m crystal oscillator input RST_N; / / reset port for the development board, low-level reset output LED1; / / corresponding to the LED on the development board

/ /-/ /-- Internal port declaration / /- -reg [26:0] time_cnt / / timer counter reg led_reg; / / used to control the flicker frequency of LED / / display register used to control the flicker of LED / / the time to set the timer is 1s. The calculation method is (1 * 10 ^ 6) us / (1 us 50MHz 50) us 50MHz is the development board crystal oscillator / / parameter SET_TIME_1S = 270d499999999; parameter SET_TIME_1S = 27'd49 / / for simulation /-/-logical function implementation / /- -Sequential circuit Implement 1s timing counter always @ (posedge CLK_50M or negedge RST_N) begin if (! RST_N) / / judge reset time_cnt

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