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This article will explain in detail how to understand the IIC bus specification of the IIC protocol. The content of the article is of high quality, so the editor shares it for you as a reference. I hope you will have some understanding of the relevant knowledge after reading this article.

FPGA implementation of 1 IIC protocol

1.1 introduction to IIC bus specification 1) introduction to IIC bus characteristics

In the process of modern electronic product development,    has introduced an efficient, reliable and convenient IIC serial bus in order to simplify the system, improve the reliability of the system, shorten the product development cycle and increase the flexibility of hardware composition. The two-wire IIC serial bus makes only a simple two-wire connection between the circuit units, and the bus interfaces are integrated in the device, which can realize the modular and standardized design of the circuit system. On the IIC bus, each unit circuit has no other connection with each other, and the commonly used unit circuit basically has nothing to do with the system circuit, so it is easy to form its own standardized and modular design.

2) IIC standard mode bus specification

The   IIC bus can be connected to any device on the bus through serial data (SDA) and serial clock (SCL) lines. Each device has a unique address and can be used as a transmitter or receiver. Each device can also be regarded as a host or slave when performing data transmission.

A device that transmits data (excluding addresses and commands) to the bus.

A device that receives data (excluding addresses and commands) from the bus in this transmission.

A device that initializes transmission, generates clock signals, and terminates transmission. It can be a transmitter or receiver, and the host is usually a microcontroller.

The slave is a device addressed by the host, which can be a transmitter or receiver.

   IIC bus is a multi-host bus, which can connect multiple devices that can control the bus to the bus. When more than two devices that can control the bus are transmitted at the same time, only one device can really control the bus and become the host, and the message will not be destroyed. This process is called arbitration. At the same time, a plurality of devices capable of controlling the bus can generate synchronous clock signals.

Both    SDA and SCL are bi-directional lines, and the output stage of the device connected to the bus must be drain open circuit or collector open circuit. The device is connected to the positive power supply voltage through a current source or pull-up resistor to realize the line and function. When the bus is idle, both lines are high. The data transmission rate on IIC bus can reach 100kb/s in standard mode, 400kb/s in fast mode and 3.4Mb/s in high speed mode. The number of interfaces connected to the bus is determined by the bus capacitance which is the limit of 400pF.

3) key points of IIC bus circuit design

  figure 21 I2C bus circuit design essentials

4) bit transmission

A clock pulse must be generated for each data bit transmitted on the    IIC bus.

The validity of    (1) data. The data on the SDA line must be stable during the high-level cycle of the clock line SCL, and the level state of the data line can only be changed when the clock signal of the SCL line is low, as shown in figure 2.11. In standard mode, the high and low level width must be greater than or equal to 4.7us.

  figure 2 data validity

  figure 2 3 bit transmission controlled by IIC bus

   (2) start and stop conditions. On the IIC bus, the only violations of the validity of the above data are the start (S) and stop conditions, as shown in figure 24.

   start condition (repeat start condition): when the SCL line is high, the SDA line switches from high level to low level.

   stop condition: when the SCL line is high, the SDA line switches from low level to high level.

         figure 2 4 start bit and stop condition

   start and stop conditions are generally generated by the host. The starting condition is as the beginning of a transmission, after which the bus is considered to be busy. The stop condition is the end of a transmission, and after a certain period of time of the stop condition, the bus is considered to be idle again. The repeat start condition serves as both the end of the last transmission and the beginning of the next transmission.

5) data transmission

   (1) byte format. Each byte sent to the SDA line must be 8 bits. There is no limit to the number of bytes that can be sent per transmission, and each byte must be followed by a reply bit. The first thing to transmit is the highest bit (MSB) of the data, as shown in figure 25.

         figure 2 5 data transmission of IIC bus

   (2) reply. The corresponding response clock pulse is generated by the slave computer. During the answered clock pulse, the transmitter releases the SDA line (high). At the same time, the receiver must lower the SDA line so that it maintains a stable low level during the high level of the clock pulse, as shown in figure 25. The 9th bit of the clock signal SCL.

   generally speaking, a slave that is addressed or a receiver that can continue to receive the next byte will produce a reply. If the host as the sender does not receive a reply bit (or a non-reply bit) after sending a byte, or if the host as the receiver does not send a reply bit (or sends a non-reply bit), then, the host must generate a stop condition or a repeat start condition to end the wooden transmission. If the slave (receiver) cannot receive more data bytes, this response bit will not be generated: the host (receiver) does not respond after receiving the last byte and notifies the slave (sender) of the end of the data.

6) Arbitration and clock generation

   (1) synchronization. Clock synchronization is achieved by connecting each clock-producing device "line and" to the SCL line. Each device may have its own independent clock. The frequency, period, phase and duty cycle of each clock signal may be different. Due to the result of "line and", the low-level width of the actual clock generated on the SCL line is determined by the device with the longest duration of the low level. His high level width is determined by the device with the shortest duration of the high level.

   (2) arbitration. When the bus is idle, multiple hosts start the transmission at the same time, and it is possible to detect that more than one host satisfies the starting condition and obtains the host right at the same time, which requires arbitration. When the SCL line is high, arbitration occurs on the SDA line, and when other hosts send low levels, the host that sends the high level will lose the arbitration because the level on the bus is different from its own.

Arbitration can last multiple bits, and its first stage is to compare address bits, and if each host tries to address the same device, the arbitration continues to compare data bits, or compare response bits. Because the address and data information of the IIC bus is determined by the host that wins the arbitration, the information will not be lost during the arbitration.

   (3) uses clock synchronization mechanism to make pseudo handshake. The device can quickly receive data bytes, but it may take more time to save the received bytes or prepare a byte to be sent. At this point, the device can keep the SCL line low, forcing the device with which the data is exchanged to wait until the next byte is ready to send or receive.

7) Transport protocol

   (1) addressing bytes. After the host generates the starting condition, the first byte sent is the addressing byte. The first 7 bits (the highest 7 bits) of the byte are the slave address, and the lowest bit (LSB) determines the direction of the message. "0" indicates that the host writes to the slave, and "1" indicates that the host reads the information in the slave, as shown in figure 2.14. When an address is sent, each device in the system compares the first seven bits with its own address. If the same, the device will answer the addressing of the host, and whether the slave-receiver or slave-transmitter is determined by the R / W bit.

      figure 26 the first byte after the starting condition

The    slave address consists of a fixed part and a programmable part. For example, if some devices have 4 fixed bits (high 4 bits) and 3 programmable address bits (low 3 bits), a total of 8 identical devices can be connected on the same bus. The IIC bus Committee coordinates the allocation of IIC addresses and retains two groups of 8-bit addresses (0000XXX and 1111XXX). The purpose of these two groups of addresses can be consulted.

   (2) transmission format. After the host produces the starting condition, it sends an addressing byte, and the receipt of the reply is followed by data transmission, which is usually terminated by the stop bit generated by the host. However, if the host still wants to communicate on the bus, it can generate a repeat start condition (Sr) and address another slave instead of first producing a stop condition. In this kind of transmission, there may be different combinations of read / write formats.

   data can be transferred in the following three formats:

The   ① host-transmitter sends data to the slave-receiver, as shown in figure 2.15. The "Rbig W" bit of the addressed byte is 0, and the direction of data transmission remains unchanged.

After the   ② addresses the byte, the host-receiver immediately reads the data in the slave-transmitter, as shown in figure 2.16. The RUnip W bit of the addressed byte is 1. When the first slave produces a response, the host-transmitter becomes the host-receiver and the slave-receiver becomes the slave-transmitter. After that, the data is sent by the slave and received by the host. Each reply is generated by the host, and the clock signal CLK is still generated by the host. If the host wants to terminate the transmission, a non-reply signal (/ A / A) is sent, and then the host generates a stop condition.

      figure 2 7 Host-sender sends data

         figure 2 8 after addressing bytes, the host-receiver reads the data immediately

The   ③ composite format is shown in figure 2.17. When the transmission changes direction, both the starting condition and the slave address are repeated, but the bits are reversed. If the host-receiver sends a repeat start condition, it should send a non-reply signal (/ A) before.

      figure 2 9 compound format

By default in   , the device address is eight bits wide, so the device address is also known as the device byte. The top four digits of the device address, that is, [7 … 4] record the hardware ID, followed by three digits, that is, [3 … 1] the hardware address is recorded, and the last bit is the access direction of the device. The results are shown in Table 21:

   's so-called hardware ID is the identification ID of IIC devices, and the hardware ID will change with the manufacturer and the type of equipment. The IIC device on the development board is a manufacturer's IIC storage, namely 24LC04, and the hardware ID is 4'b1010. As for the hardware address, which is identified by IIC devices on the bus, it is 3 bits by default, that is, similar IIC devices are only allowed to occupy 8 on the same IIC bus. However, the 24LC04 on the development board is 3'b000. The last access direction bit is used by the host to notify the slave, and the purpose of the access is to read or write.

To sum up, except for the access direction, the first seven bits of the device address are generally fixed, such as the IIC memory 24LC04 of the common development board, and the device address is 8roomb1010000x.

      figure 2 10 24LC04 write operation (host perspective)

The timing of the    IIC bus feels like a bunch of jigsaw puzzles. As shown in figure 210, that is the write operation of 24LC04. The sequence is first filled in as the starting bit, then the device address, the rest is the reply bit, followed by the data address, then the reply bit, then the write such as data, the reply bit again, and finally the end bit is hung to indicate that the one-time write operation has been completed. So, the process of writing is as follows:

(1) start bit sent by the host

(2) the address of the host sending equipment (write)

(3) waiting for the slave to reply

(4) the address of data sent by the host

(5) waiting for the slave to reply.

(6) data sent by the host

(7) waiting for the slave to reply

(8) the host sends the end bit.

   pays a little attention to the lowest bit of the device address. Since this is a write operation, the access direction of the device address is "write", so the access direction bit is set to 0.

         figure 2 11 24LC04 read operation (host perspective)

Figure 211 of    shows the reading sequence of 24LC04, which is also made up of a bunch of "puzzles". Compared with the write operation, the read operation not only has many "puzzles", but also changes the direction of access along the way. So, the read operation goes through the following:

(1) start bit sent by the host

(2) the address of the host sending equipment (write)

(3) waiting for the slave to reply

(4) the address of data sent by the host

(5) start bit of host transmission

(6) the address of the host sending device (read)

(7) waiting for the slave to reply

(8) data read by the host computer

(IX) there is no answer from the slave (the host ignores the reply)

(10) the host sends the end bit.

The data transfer rate on    IIC bus can reach 100kb/s in standard mode, 400kb/s in fast mode and 3.4Mb/s in high speed mode. Experiment 16 will use the rate of 400Khz as the standard. The number of interfaces connected to the bus is determined by the bus capacitance which is the limit of 400pF. Here, the experiment will take the rate of 400Khz as the standard.

   must consider the timing of the chip when performing IIC timing analysis, as shown in the following table:

      figure 2 12 timing table of chip 24LC04

   IIC bus is a serial transmission protocol, which includes both clock signal SCL and data signal SDA. Clock Frequency represents the frequency of the SCL signal, Clock High Time represents the minimum time it takes for the SCL signal to remain high, and Clock Low Time represents the minimum time it takes for the SCL signal to remain low.

   as for Rise Time and Fall Time said that the SCL signal also has the minimum time required for the SDA signal to change from high to low or from low to high, that is, uphill and downhill time. Hold Time and Setup Time are the timing parameters used to evaluate whether data is successfully entered into the register, which is typical of the typical ones. Setup Time represents the setup time, which is the stabilization time required before the data is written into the register; conversely, Hold Time is the hold time, that is, the stabilization time required after the data is entered into the register. As long as both are met, the storage of data is ensured.

   Start is the start bit of IIC bus, Stop is the end bit of IIC bus, and Data is the data bit of IIC bus. In order to ensure that the three are successfully written to the slave, Setup Time and Hold Time must be satisfied. Ouput Valid FromClock is the timing parameter of relational data bits, and Bus Free Time is the timing parameter of relational end bits. In addition, in order to simplify the timing, the author converts the actual time of various parameters into the results after 50Mhz quantization. Interpret the above table as follows:

Clock Frequency, which is both frequency and speed, in this case, 400Khz.

Clock High Time, the minimum time required for the SCL signal to remain high.

Clock Low Time, the minimum time required for the SCL signal to remain low.

Rise Time, the maximum time required for the signal to change from bottom to high.

Fall Time, the minimum time required for both high and low signal.

Start Hold Time, the minimum holding time required to start the bit.

Start Setup Time, the minimum setup time required to start the bit.

Data Input Hold Time, the minimum retention time required for data bits.

Data Input Setup Time, the minimum set-up time required for data bits. 

Stop Setup Time, the minimum hold time required for the end bit.

Ouput Valid From Clock, the effective time after the data bit is triggered by the clock edge.

Bus Free Time, the minimum time to release the bus.

This is the end of the IIC bus specification on how to understand the IIC protocol. I hope the above content can be helpful to everyone and learn more knowledge. If you think the article is good, you can share it for more people to see.

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