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Editor to share with you what are the skills of verilog, I believe that most people do not know much about it, so share this article for your reference, I hope you can learn a lot after reading this article, let's go to know it!

1the difference between wire and wire:

Similarities:

Can represent a type.

Differences:

Wire

Wired data, network type

Represents the physical connection between components and cannot save data

The wire network is driven and can be driven by continuous assignment statements or connecting the output of the element to the wire network.

The value element that provides the driver to the wire network is the "driver source", and the value of the wire network is determined by the driver source.

If the wire network is not connected to the driver source, the default value is "Z".

Reg:

A register data type, usually used to describe a storage unit

Such variables can maintain their own values until the variable is assigned a new value; the variable assigned in the procedure must be defined as regal

Only unsigned numbers can be stored.

Signed number register variable: integer.

2. Dint stop:

Indicates a stop command, in a common format, in an initial statement:

# time (N) $stop

Indicates that the simulation is stopped after (N) units of time.

3. Parameter declaration parameter:

When you need to use the same number many times in the program, you can consider using parameters to improve the simplicity of the code and reduce the amount of code design.

Once a parameter is declared, it is treated as a constant and the value does not change throughout the process.

It is defined as follows:

=

For example:

Parameter SET_TIME_1S=27'b50_000_000

Replace the constant 50000000 with the identifier SET_TIME_1S.

When multiple parameters are defined at the same time with the same parameter, the parameters are separated by ",".

Using parameters can improve the readability of the code and make it easy to modify.

4, Port definition during simulation

The signal port connected to the module input port is the port that generates the simulation signal and needs to be defined as the reg type.

The signal port connected to the module output port is the port driven by the output signal and needs to be defined as a wire type.

5, blocking and non-blocking assignment statements

1, non-blocking assignment statement

With operators. "

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