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This article mainly introduces how the STM32 network circuit design is, has a certain reference value, interested friends can refer to, I hope you can learn a lot after reading this article, the following let the editor take you to understand it.

Area 1: we call it the SMI interface, which is used to configure external PHY chips.

Area 2: is the data exchange interface, that is, the MII interface and RMII interface we mentioned above.

There are many different network circuit designs using these interfaces, which I would like to summarize here.

01. MII interface scheme

The MII interface has been described in detail in the article "MII and RMII of STM32 Networks", from which we know that a 25MHz clock is needed.

For the MII interface, the most commonly used scheme is to connect the STM32 with the crystal oscillator of the 25MHz.

Internal PLL configuration HCLK, provided to the kernel and peripherals, and so on.

The external PHY connection provides the MCO pin of the 25MHz.

This scheme is suitable for STM32F107/2x7/4x7.

02. RMII interface scheme

The RMII interface has been described in detail in the article "MII and RMII of STM32 Networks", from which we know that a 50MHz clock is needed.

2.1. External crystal oscillator (2 crystal oscillators)

This scheme requires two crystal oscillators connected to each other.

External 25MHz crystal oscillator, internal PLL configuration HCLK, provided to the kernel and peripherals, etc.

External 50MHz crystal oscillator, output 50MHz clock, provided to MAC controller and external PHY.

This scheme is suitable for STM32F107/2x7/4x7.

2.2. External crystal oscillator (1 crystal oscillator)

In this scheme, only one 50m crystal oscillator is needed. A crystal oscillator provides clocks for both the STM32 and the external PHY, which saves costs.

Important: STM32F2X7 cannot use this scheme, it only applies to STM32F107/4x7.

Pay attention to the difference in the picture above.

This is because the OSC part of HSE is filtered out, and through the bypass of HSE, the clock of 50MHz has been input to PLL through OSCIN, and then the clock that provides kernel and peripherals is generated through PLL.

2.3.The need for strong PHY

This scheme also uses a 25MHz crystal oscillator, but requires a powerful PHY chip, which can double the internal frequency of the input 25MHz clock to the 50MHz clock and then output it to the MAC control module of STM32.

External 25MHz crystal oscillator, internal PLL configuration HCLK, provided to the kernel and peripherals, etc.

STM32 provides the 25MHz clock to the external PHY through the MCO pin.

The clock of the external PHY that generates the 50MHz is provided to the MAC control module of the STM32.

This scheme is suitable for STM32F107/2x7/4x7.

Personally, this scheme is not recommended, which is not conducive to the replacement of materials in the later stage.

Thank you for reading this article carefully. I hope the article "what the STM32 network circuit design is like" shared by the editor will be helpful to everyone. At the same time, I also hope that you will support us and pay attention to the industry information channel. More related knowledge is waiting for you to learn!

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