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How to understand Primitives and Macros in Xilinx? aiming at this problem, this article introduces the corresponding analysis and solution in detail, hoping to help more partners who want to solve this problem to find a more simple and feasible way.

Source language (Primitives)-the simplest design element in the Xilinx library. Primitives primitives are design elements "atoms". Examples of Xilinx primitives include a simple buffer BUF and a D trigger FDCE with clock enabling and clearing capabilities.

Macros (Macros)-the design element "molecule" of the Xilinx library. You can create macros from design element primitives or macros. For example, a FD4CE trigger macro is a combination of four FDCE primitives.

1 Source language classification

Xilinx primitives are divided into 10 categories, including: computing components, IO port components, registers / latches, clock components, processor components, shift registers, configuration and detection components, RAM/ROM components, Slice/CLB components, G-tranceiver. For a more detailed description of specific primitive resources, please refer to the documents UG799 and UG768.

2 Source language call

1 > Open PROJECT MANAGER-- > Language Templates

2 > most of the language templates are shown in figure 5 below

3 > Select the corresponding device type and module assembly.

4 > BUFG example

/ / BUFG: In order to incorporate this function into the design

/ / Verilog: the following instance declaration needs to be placed

/ / instance: in the body of the design code. The instance name

/ / declaration: (BUFG_inst) and/or the port declarations within the

/ / code: parenthesis may be changed to properly reference and

/ /: connect this function to the design. All inputs

/ /: and outputs must be connected.

/ /

/ / BUFG: Global Clock Simple Buffer

/ / Kintex-7

/ / Xilinx HDL Language Template, version 2019.1

BUFG BUFG_inst (

.O (O), / / 1-bit output: Clock output

I (I) / / 1-bit input: Clock input

);

/ / End of BUFG_inst instantiation

3 BUFG

Primitive: Global Clock Simple Buffer

Introduction:

The design element is a high fan-out buffer that connects signals to global routing resources to achieve low skew distribution of signals. BUFG is commonly used in clock networks and other high fan-out networks, such as set / reset and clock enable.

Port description:

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