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Static timing analysis and setup and hold timing violation repair example analysis, many novices are not very clear about this, in order to help you solve this problem, the following editor will explain for you in detail, people with this need can come to learn, I hope you can gain something.

STA is used to analyze whether all timing paths in the design are timing convergent, which does not require input excitation. For digital chip design engineers, it is necessary to understand different timing paths and related STA concepts.

Timing analysis is applicable to any stage of ASIC design and can be performed at all design stages. If the design violates setup time or hold time, the design enters metastability.

Therefore, the timing violation in the design must be found and solved through the timing analysis tool Synopsys PT.

Setup Time& Hold Time

The minimum time required for the trigger input signal'd'to maintain a stable value before the effective clock edge arrives is called setup time (setup time).

The time that the trigger input signal'd' should hold at least after the effective edge of the clock arrives is called hold time (hold time).

Frequency Calculations

As shown in the following figure, the timing parameters of reg1 are tpff1 and tsu1, and the timing parameters of reg2 are tpff2 and tsu2. The combinational logic delay in this data path is tcomb. These timing parameters can be used to determine the maximum operating frequency of the design.

Arrival time is tpff1 + tcomb,required time is Tclk-tsu2, where Tclk is the clock cycle and tsu2 is the setup time of the second trigger.

Therefore, the calculation of the maximum frequency needs to meet:

Tpff1 + tcomb = Tclk-tsu2 Tclk = tpff1 + tcomb + tsu2 Fmax = 1 / (tpff1 + tcomb + tsu2)

Skew in Design

In the figure above, trigger 1 is launchflip-flop and trigger 2 is capture flip-flop.

In the above example, the buffer delay is increased on the clock path. At this point, the maximum frequency is:

Tpff1 + tcomb = Tclk-tsu2+tbufTclk = tpff1 + tcomb + tsu2- tbuf Fmax = 1 / (tpff1 + tcomb + tsu2- tbuf)

In the above example, buffer latency is increased on the data path. At this point, the maximum frequency is:

Tpff1 + tcomb + tbuf= Tclk-tsu2Tclk = tpff1 + tcomb + tsu2+ tbufFmax = 1 / (tpff1 + tcomb + tsu2+tbuf)

From this, it can be seen that the skew on the data path and the clock path will affect the performance of the design from the opposite direction.

Timing Paths in Design

STA determines whether the ASIC design is a timing violation by checking all possible timing paths in the design, and only checks the paths with the worst delay, regardless of the logic function of the design.

The timing path starts from the register clock port or input port, which is called Start point.

The timing path terminates at the register data port or output port, called Endpoint.

For any RTL design, there can be four types of temporal paths:

Input-to-register path Output-to-register path Register-to-register path Input-to-output path

Timing Goals for the Design

In the actual scenario, clock and IO timing are used to define the timing goal of the design. Because after defining the clock, it means that Register-to-register path is defined.

Min-Max Analysis for ASIC Design

Setup time Min-Max analysis is based on the fastest clock arrival and the slowest data arrival.

Hold time Min-Max analysis is based on the fastest data arrival and the slowest clock arrival.

For fix setup time violations, the data should arrive quickly, the launch clock should arrive quickly, and the capture clock should arrive slowly.

For fix hold time violations, the data should arrive slowly, the launch clock should arrive slowly, and the capture clock should arrive quickly.

Here are two examples of optimizing setup time and hold time, respectively:

Setup Violation Fix

Now the popular coding techniques are priority coding (priority encoding) and multiplexing coding (multiplexed encoding).

Assign y_out=a_in & & baked inmates & c_in & & d_in & & e_in & & favored inmates & galleys & h_in

The above statement generates priority logic, where h_in has the highest priority.

In the priority coding method, the total delay is 7tpd. In order to improve the design performance, the propagation delay of combinational logic must be reduced.

The following figure shows the multiplexing code, and the total propagation delay is only 3tpd. (the embodiment of parallelization)

Hold Violation Fix

For the design in the figure above, a hold time violation may occur if the combinational logic delay is small.

To fix a design hold time violation, you can insert a buffer on the data path, but be careful not to cause a build time violation.

Timing Exceptions in the Design

1 、 Asynchronous and False Paths

If the change of a signal or port in the design does not affect the output, it needs to be set to false path.

Asynchronous paths are also considered false path and do not require timing checking.

2 、 Multicycle Paths

If the timing path delay in the design allows more than one clock cycle, the path is considered a multi-cycle path.

Set_multicycle_path-setup 2-from [get_cells FF4]-to [get_cells FF5] set_multicycle_path-hold 1-from [get_cells FF4]-to [get_cells FF5] is it helpful for you to read the above content? If you want to know more about the relevant knowledge or read more related articles, please follow the industry information channel, thank you for your support.

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