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This article mainly introduces the example analysis of i2s input and output in FPGA karaoke system, which has a certain reference value. Interested friends can refer to it. I hope you will gain a lot after reading this article.

1 introduction of hardware requirements

Figure 1 Karaoke hardware system

1) microphone (microphone)

2) Audio ADC-PCM1080 or other audio ADC

3) FPGA-karaoke system

4) Audio DAC--PCM5102A

5) Audio

6) display screen

2 introduction to audio ADC DAC

1) Audio adc--pcm1080

PCM1808 single-ended, 24-bit analog input, 96kHz stereo ADC.

Performance:

-THD + NRV muri 93 dB (typical value)

-SNR:99 dB (typical)

-dynamic range: 99 dB (typical)

Oversampling decimation filter:

-oversampling frequency: × 64

-passband ripple: ±0.05dB

-stopband attenuation:-65 dB

-on-chip high-pass filter: 0.91 Hz (48 kHz)

PCM Audio Interface:

-Master mode or slave mode is optional

-data format: 24-bit i2Scripts 24-bit left alignment

Sampling rate: 8 kHz-96 kHz

Fig. 2 PCM1080 block diagram

2) Audio dac--PCM5102a:

The PCM510xA 2.1 VRMS,112/106/100 dB audio stereo DAC has PLL and a 32-bit 384kHz PCM interface.

Dynamic range of PCM510xA, performance of SNR and THD:

Fig. 3 PCM5102A block diagram

3 introduction of FPGA hardware system

Fig. 4 fpga internal audio algorithm system

After audio adc acquisition, audio analog signal is converted into digital signal and sent to FPGA,FPGA through I2S. It can be used as equalizer algorithm, feedback suppression algorithm, reverberation echo of high and low pass filter and audio processing algorithm of changing sound.

4reception and transmission of i2s

1) Overview of i2s

I2S (Inter-IC Sound) bus, also known as integrated circuit built-in audio bus, is a bus standard developed by Philips for audio data transmission between digital audio devices. This bus is specially used for data transmission between audio devices and is widely used in various multimedia systems. I2S adopts the design of transmitting clock and data signals along independent wires. By separating the data and clock signals, I2S avoids the distortion caused by time difference and saves users the cost of purchasing professional equipment to resist audio jitter.

In the Philips I2S standard, I2S has three main signals.

1. Bit clock BICK (also known as serial clock SCLK), that is, every bit of data corresponding to digital audio, BCLK has a pulse. The frequency of BCLK is 2 × sampling frequency × number of sampling bits.

two。 The frame clock LRCK, also known as WS, is used to switch data between the left and right channels. A LRCK of "1" indicates that data is being transmitted from the right channel, and a value of "0" indicates that data from the left channel is being transmitted. The frequency of LRCK is equal to the sampling frequency.

3. Serial data SDATA is the audio data represented by binary complement.

Sometimes in order to achieve better synchronization between systems, it is necessary to transmit an additional signal MCLK, called master clock, also known as system clock (Sys Clock), which is 256x or 384x of the sampling frequency. With the development of technology, there are many different data formats under the unified I2S interface. According to the position of SDATA data relative to LRCK and SCLK, it is divided into left alignment (less used), I2S format (Philips format) and right alignment (also known as Japanese format, common format).

The following is a partial series of I2S Sample rate 44.1Khz and 48Khz.

2) Model

Left alignment mode: SDATA's MSB gets the first rise in BCLK according to LRCK's transmission.

I2S mode: the MSB of SDATA gets the transmission according to LRCK in the second rise of BCLK.

Right alignment mode.

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