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Editor to share with you what is the use of STM32 basic timer, I believe most people do not know much about it, so share this article for your reference, I hope you can learn a lot after reading this article, let's go to know it!

The most basic function of a timer is to handle things on a regular basis. For example, regularly send USART data, regularly collect AD data, regularly detect the potential of the IO port, and output waveforms through the IO port. Can achieve a very rich function. Timer is a very powerful peripheral, which is used in different ways in different industries and has a wide range of knowledge.

01. Introduction of timer

First of all, we can find the resources of the customizer in the STM32F207 data manual. From the following figure, you can see that STM32F207 has a total of 10 general timers, 2 advanced timers, and 2 basic timers.

The difference between different timers

The basic block diagram of the timer can be seen in the STM32F207 user reference manual. the following picture shows the timer 1: 8.

① CK_PSC is the timer clock TIMxCLK, which is provided by APB1 prescaler and frequency division.

After the ② timer clock passes through the PSC prescaler, the CK_CNT is used to drive the counter count.

③ counter CNT is a 16-bit counter, up, down, up / down count mode, the maximum count value is 65535. An update event is generated when the count reaches the automatic reload register, and the count is cleared from scratch.

The ④ automatic reload register ARR is a 16-bit register that contains the maximum number that the counter can count. When counting to this value, the timer generates an overflow interrupt if the interrupt is enabled.

To put it bluntly, the timer is a counter, just as we roughly estimate the time with the heartbeat, the heartbeat can be roughly thought of as 1s, so we timed 60 heartbeats for 60 seconds. The CK_CNT clock is similar to the heartbeat, and the CNT counter is similar to the heartbeat times. To take an extremely simple example, we want to achieve 60 second timing, CK_CNT is 1s, we set the CNT counter to count up to turn on the interrupt, because only when the overflow, that is, count to 65535, there will be an interrupt, then we set the CNT counter to 65535-60 seconds 65475, start in time, then 60 seconds later there will be an interrupt. We set the automatic reload register ARR to 65475. When the CNT counter overflows, the automatic reload register ARR will be automatically loaded into the CNT counter, and the automatic cycle timing can be achieved for 60 seconds.

After the above analysis, the key to accurate timing is the frequency of the CK_CNT, and the CK_CNT is divided by the timer clock. Then we need to know timer3's timer clock. We will look at the clock system part, specifically look at the article "STM32F207 clock system Analysis", this article mainly explains how the 120m clock of the system is obtained from the external 25m crystal oscillator. It talks about the problem of APB peripheral clock.

The timer is under the APB timer clock, specifically under the APB1 or APB2 clock. We can see the picture name STM32F20xblock diagram in the STM32F207 data manual.

From the above, we can see that timer3 is under APB1.

So let's analyze the frequency of APB1.

As can be seen from the picture above, the APB1 timer is obtained from the system 120m clock (the system clock is configurable, we use the default 120m clock) through AHB frequency division, APB frequency division.

Speaking of the "mistake" in the red box above, Mengxin may not quite understand it. First of all, there is a missing closing parenthesis in the manual. After modification, it should be:

If (APBx presc = = 1) X1else X2

That is to say

If the APB frequency division factor is 1 and the frequency is constant, the frequency of the APB output is the frequency of the clock under APB.

The frequency division factor of APB is not 1. The frequency of the output of X2Go APB multiplied by 2 is the frequency of the clock under the APB.

Let's analyze the APB1 clock, from the SetSysClock function in system_stm32f2xx.c as follows

/ * HCLK = SYSCLK / 1 PCLK1 RCC-> CFGR | = RCC_CFGR_HPRE_DIV1; / * PCLK2 = HCLK / 2 HCLK RCC-> CFGR | = RCC_CFGR_PPRE2_DIV2; / * PCLK1 = HCLK / 4 matching RCC-> CFGR | = RCC_CFGR_PPRE1_DIV4

It can be seen that the AHB frequency division coefficient is 1 and the APB1 frequency division coefficient is 4.

The clock of the timer3 is 120m Compact 1max 4pm 2 = 60MHZ.

There is a question as to why the system_stm32f2xx.c comments provided by ST are HCLK,PCLK2,PCLK1, but there is no APB,AHB word mentioned above. Take a look at my previous article, "STM32F207 clock system parsing."

In fact, we have the analysis code, and the system_stm32f2xx.c file header is also annotated, which is easy to view.

Of course, this requires that our external crystal oscillator is 25m, and the system_stm32f2xx.c has not been modified, if you need to modify this file MCU overclocking operation, it is recommended to modify the notes of the file header to develop a good habit.

03. Time base unit

The programmable advanced timer control module is mainly a 16-bit counter with related automatic overload. This counter can be counted up, down, or alternately increasing and decreasing. The counter clock can be divided by a frequency divider.

The automatic overload register and pre-division register of the counter can be read and written by software. You can read and write even when the counter is running.

Time base units include

Counter register (TIMx_CNT)

Prescaler register (TIMx_PSC)

Automatic overload register (TIMx_ARR)

Repetitive counter register (TIMx_RCR)

The automatic overload register is preloaded. Writing or reading from the automatic overload register accesses the preload register. The contents of the preload register can be transferred either directly to the shadow register or to the shadow register each time an update event (UEV) occurs, depending on the automatic reload enable bit (ARPE) in the TIMx_CR1 register. When the counter reaches the upper overflow value (or the lower overflow value when decreasing the count) and the UDIS bit in the TIMx_CR1 register is 0, an update event is sent. The update event can also be generated by the software.

The counter is provided with a clock by the prescaler output CK_CNT, and starts only when the counter start bit (CEN) in the TIMx_CR1 register is set to 1.

Description of prescaler

The prescaler can divide the counter clock frequency, and the frequency division coefficient is between 1 and 65536. The prescaler is based on a 16-bit counter controlled by a 16-bit register in the TIMx_PSC register. Because the control register has a buffering function, the prescaler can be changed in real time. The new pre-division ratio will be used when the next update event occurs.

The following figure illustrates the behavior of the counter when the pre-division ratio changes in real time.

Counter sequence diagram when frequency division of prescaler is changed from 1 to 2

Counter sequence diagram when the frequency division of prescaler is changed from 1 to 4

04, count mode 4.1, up count mode

In the up count mode, the counter is incremented from 0 to the automatic overload value (the value of the TIMx_ARR register), then starts again from 0 and generates a counter overflow event.

If a repeat counter is used, an update event (UEV) is generated when the number of iterations of the increment count reaches the number of times programmed in the repeat counter register (TIMx_RCR+1). Otherwise, an update event is generated each time the counter is overflowed.

An update event is also generated when the UG location 1 of the TIMx_EGR register is passed through the software or using the slave mode controller.

The UEV event can be disabled by setting UDIS location 1 in the TIMx_CR1 register by the software. This avoids updating the shadow register when a new value is written to the preloaded register. No update event occurs until the UDIS bit is written to 0. However, both the counter and the prescaler counter re-count from 0 (while the prescaler ratio remains the same). In addition, if the URS bit (update request selection) in the TIMx_CR1 register is set to 1, setting the UG location 1 generates an update event UEV, but does not set the UIF flag to 1 (therefore, no interrupts or DMA requests are sent). In this way, if the counter is cleared to zero when a capture event occurs, there will be no update interrupt and capture interrupt at the same time.

When an update event occurs, all registers are updated and the update flag (UIF bit in the TIMx_SR register) is set to 1 depending on the Urs bit)

The contents of the TIMx_RCR register will be reloaded in the repeat counter

The automatic overload shadow register will be updated with the preloaded value (TIMx_ARR)

The preload value (contents of the TIMx_PSC register) will be reloaded in the buffer of the prescaler

Counter sequence diagram, 1 division internal clock

Counter sequence diagram, 2-division internal clock

As can be seen from the above two pictures, the interrupt flag needs to be cleared by the software.

Counter sequence diagram, update event on ARPE=0 (TIMx_ARR is not preloaded)

As you can see from the above two figures, if you change the automatic overload register to 0x36 before you reach 0x36, an action will occur when counting to 0x36.

Counter sequence diagram, update event on ARPE=1 (TIMx_ARR preload)

As can be seen from the above two figures, if you change the automatic reload preload register to 0x36 before you reach 0x36, there will be no action when counting to 0x36. At this time, the automatic overload preload register value will be assigned to the automatic reload shadow register.

4.2. Downward counting mode

In the down count mode, the counter counts down from the automatic overload value (the value of the TIMx_ARR register) to 0, then from the automatic overload value (restart) and generates a counter overflow event.

If a repeat counter is used, an update event (UEV) is generated when the number of repetitions of the decrement count reaches the number of times programmed in the repeat counter register (TIMx_RCR+1). Otherwise, an update event is generated each time the counter is overflowed.

An update event is also generated when you set the UG location 1 of the TIMx_EGR register (through the software or using the slave mode controller).

The UEV update event can be disabled by setting UDIS location 1 in the TIMx_CR1 register by the software. This avoids updating the shadow register when a new value is written to the preloaded register. No update event occurs until the UDIS bit is written to 0. However, the counter starts counting again from the current automatic reload value, while the prescaler counter starts counting again at 0 (but the pre-division ratio remains the same).

In addition, if the URS bit (update request selection) in the TIMx_CR1 register is set to 1, setting the UG location 1 generates an update event UEV, but does not set the UIF flag to 1 (therefore, no interrupts or DMA requests are sent). In this way, if the counter is cleared to zero when a capture event occurs, there will be no update interrupt and capture interrupt at the same time.

When an update event occurs, all registers are updated and the update flag (UIF bit in the TIMx_SR register) is set to 1 (depending on the URS bit):

The contents of the TIMx_RCR register will be reloaded in the repeat counter

The preload value (contents of the TIMx_PSC register) will be reloaded in the buffer of the prescaler

The automatic reload activity register will be updated with the preloaded value (the contents of the TIMx_ARR register). Note that the automatic overload register is updated before the counter is overloaded, so the next count cycle is the desired new cycle length.

The following figures show some examples of the behavior of counters at different clock rates when TIMx_ARR=0x36

Counter sequence diagram, 1 division internal clock

Counter sequence diagram, 2-division internal clock

Counter sequence diagram, update events when duplicate counters are not in use

4.3, Center alignment (up / Down count mode)

In center alignment mode, the counter counts from 0 to the automatic overload value (the contents of the TIMx_ARR register)-1, generating a counter overflow event; then counting down to 1 from the automatic overload value and generating a counter underflow event. Then recount starts at 0.

The center alignment mode is valid when the CMS bit in the TIMx_CR1 register is not "00". When a channel is configured in output mode, its output comparison interrupt flag is set to 1 in the following mode, that is, counter decrement count (center alignment mode 1 # CMS = "01"), counter increment count (center alignment mode 2 # CMS = "10"), and counter increment / decrement count (center alignment mode 3 # CMS = "11").

In this mode, the DIR direction bit of the TIMx_CR1 register is not writable, but is updated by the hardware and indicates the current counter direction.

An update event is generated each time a counter overflow and underflow occurs, or an update event can be generated by using UG location 1 in the TIMx_EGR register (through the software or using the slave mode controller). In this case, the counter and the prescaler counter will start counting again from 0.

The UEV update event can be disabled by setting UDIS location 1 in the TIMx_CR1 register by the software. This avoids updating the shadow register when a new value is written to the preloaded register. No update event occurs until the UDIS bit is written to 0. However, the counter still increments and decrements the count based on the current automatic overload value.

In addition, if the URS bit (update request selection) in the TIMx_CR1 register is set to 1, setting the UG location 1 generates a UEV update event, but the UIF flag is not set to 1 (therefore, no interrupts or DMA requests are sent). In this way, if the counter is cleared to zero when a capture event occurs, there will be no update interrupt and capture interrupt at the same time.

When an update event occurs, all registers are updated and the update flag (UIF bit in the TIMx_SR register) is set to 1 (depending on the URS bit):

The contents of the TIMx_RCR register will be reloaded in the repeat counter

The preload value (contents of the TIMx_PSC register) will be reloaded in the buffer of the prescaler

The automatic reload activity register will be updated with the preloaded value (the contents of the TIMx_ARR register). Note that if the update operation is triggered by an overflow on the counter, the automatic overload register is updated before the counter is overloaded, so the next count cycle is the desired new cycle length (the counter is overloaded with new values).

The following figures illustrate the behavior of counters at different clock frequencies with some examples.

Counter sequence diagram, 1 division internal clock, TIMx_ARR = 0x6

Counter sequence diagram, 2-division internal clock

Counter sequence diagram, update event at ARPE=1 (counter underflow)

Counter sequence diagram, update event at ARPE=1 (counter overflow)

05. Basic timing code

10ms interrupt configuration code

About setting Frequency Division valu

TIM3CLK = 2 * PCLK1=2*HCLK / 4 = HCLK / 2 = SystemCoreClock / 2=60MHZ

So in the red box below is TIM3CLK.

The value here is the frequency division factor = the actual frequency of the TIM3CLK/ timer, so the timer frequency is 10000, which means the divisor is the timer frequency. A clk is 1Universe 1000s. Timing time = 1thumb 10000* timer overload value. According to the above configuration, the timer overload value is 100, that is, the timer interrupt period is = 1/10000*100=0.01s=10ms, that is, 100HZ.

If the LED light is flipped in the timer, then the LED light flashing frequency is 50Hz.

Of course, the above frequency division value can be directly assigned to 5999, and if you want to change the timer frequency to 1000, you have to recalculate it. If you follow the above method, just change the divisor to 1000.

If you see here, you will have questions. The overload value given is obviously 99, and the sub-frequency value is also minus 1. The reasons why both the frequency division value and the automatic overload period value need to be subtracted by 1 are explained below.

Automatic reload value: because it is calculated from 0, the assignment is 10, and counting from 0 to 10 is 11 times.

Frequency division value: described below in the TIMx_PSC register.

Special instructions

Clock frequency division factor

TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV2

In fact, after carefully reading the technical manual, I found that this sentence has nothing to do with the PWM output experiment, this sentence is to set the timer clock (CK_INT) frequency and digital filter (ETR,TIx) sampling frequency ratio (related to input capture), 0 indicates that the filter frequency and timer frequency are the same.

First of all, the colck_division clock division coefficient does not divide the clock frequency of the timer. We all know that there is a digital filter in input capture mode, which can filter out some frequencies by configuring registers to change its sampling frequency.

Details are explained in detail in the input capture.

We can also use the method of querying the counter to achieve accurate delay according to the characteristics of the counter of the timer.

The above is all the content of this article "what is the use of STM32 basic timer?" Thank you for reading! I believe we all have a certain understanding, hope to share the content to help you, if you want to learn more knowledge, welcome to follow the industry information channel!

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