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This article to introduce the digital display circuit Verilog HDL implementation is what it is, the content is very detailed, interested friends can refer to, I hope to help you.

Any 7-segment code tube has 128 display modes, of which the numbers 0-9 are the most useful and common. By controlling the cathode (anode) of the common anode (common cathode) digital tube, the numbers 0-9 can be displayed. Figure 11-22 shows the connection relationship between the common anode and common cathode digital tube. For multi-digit digital tubes, in practice, in order to simplify the circuit, it is often necessary to connect the anodes of all common cathode digital tubes together, connect the cathodes of all common anode digital tubes together, and control all digital tubes with multiple independent bit selections and 7 (or 8) common segments.

Assuming the bit select signal is active low, when the bit select is active, the diode segment corresponding to the segment selected 0 is illuminated. Then use FPGA to control the 4-bit 8-segment digital tube to display the numbers 1, 2, 3 and 4 respectively as follows:

When position 1 is low (all other positions are high), the first digital tube is selected, and the common segment is selected for the display of the first digital tube; when position 2 is low (all other positions are high), the second digital tube is selected, and the common segment is selected for the display of the second digital tube, and so on. In a refresh cycle T, each digital tube has 1/4T cycle time to be refreshed. In order to ensure that all 4-digit LED display does not flicker, the general refresh frequency should be greater than 5Hz. In a cycle, although each digital tube will have 3/4T time is not lit, but the speed of the selection refresh is faster, at the same time due to the afterglow characteristics of the digital tube itself, each digital tube will be refreshed before dimming, so the human eye can not feel the digital tube dimming. If the refresh frequency is less than a certain value (such as 45Hz), the human eye will feel the flicker of the digital tube. General refresh frequency between 60Hz and 1KHz, multi-digit digital tube display is ideal.

module LED_Display(

clk,seg,dq,an

);

input clk;

output [6:0]seg;//phase select:consist of ABCDEFG

output dq;//little point

output [3:0]an;//bit select

reg [15:0]count_for_clk=0;//65536

reg [6:0]seg_reg;

reg [3:0]an_reg;

assign seg=seg_reg;

assign an=an_reg;

assign dq=1;

parameter zero=7'b100_0000,//G=1

one=7'b111_1001,

two = 7'b010_0100,

three= 7'b011_0000,

four = 7'b001_1001,

five = 7'b001_0010,

six = 7'b000_0010,

seven= 7'b111_1000,

eight= 7'b000_0000,

nine = 7'b001_0000;

always @ (posedge clk)//fractional frequency counter

begin

count_for_clk

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