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This article shares with you about the ARM architecture and what the common assembly instructions are. The editor thinks it is very practical, so share it with you as a reference and follow the editor to have a look.

I. ARM architecture

  ARM (Advanced RISC Machines) can be regarded as the name of a company, a general term for a class of microprocessors, and the name of a technology. ARM processor is a 32-bit RISC processor with low power consumption and high performance. ARM-based processors are widely used because of their high speed, low power consumption and many other excellent performance.

After the classic processor ARM11,   ARM changed its name to Cortex, which is divided into A, R and M categories, which are used in different fields. The Cortex series belongs to the ARMv7 architecture, in which the "A" series is for cutting-edge virtual memory-based operating systems and user applications; the "R" series is for real-time systems; and the "M" series is for microcontrollers. Before the introduction of ARM11, its processors were compared to:

ARM7ARM9ARM10ARM11 pipeline 3 level 5 level 6 level 8 typical frequency MHz80150260335 power consumption mW/MHz0.060.19 (+ cache) 0.5 (+ cache) 0.4 (+ cache) performance MIPS/MHz0.971.11.31.2 architecture von Neumann Harvard

The difference between   von Neumann structure and Harvard structure:

  uses S3C2440 chips on the TQ2440 development board. This is a microprocessor chip based on ARM920T core, using Harvard architecture using five-level instruction pipeline including: fetch, decode, execute, store and write. The functions of each step are as follows:

(1) fetch instruction (fetch): fetches the instruction from the memory and puts it into the instruction pipeline.

(2) decode: instructions are decoded to read register operands from the register heap. There are three Operand read ports in the register stack, so most ARM instructions can read their operands in one cycle.

(3) execute: shifts one of the operands and produces the result in ALU. If the instruction is a Load or Store instruction, the address of the memory is calculated in ALU.

(4) buffer / data (buffer/data): access the data store if necessary, otherwise the ALU simply buffers 1 clock cycle.

(5) write-back: writes back the result of the instruction to the register heap, including any data read from the register.

1.1ARM basic data type

  ARM uses a 32-bit architecture, and there are three basic data types: Byte (byte), 8-bit word half word (half word), 16bit (half word must be 2-byte boundary aligned), Word (word), 32bit (word must be aligned at 4-byte boundary).

  1-word data items occupy a set of 4-byte positions that begin with an address in multiples of 4 (the last two digits of the address are 00) and the half-word occupies two bytes, starting with the even-digit address (the last bit of the address is 0).

1.2 large / small end of memory

  high-end mode means that the high bytes of data are stored in the low address of memory, while the low bytes of data are stored in the high address of memory. Small-end mode means that the high bytes of data are stored in the high address of memory, while the low bytes of data are stored in the low address of memory. For example, the variable word a=0xf6734bcd, using the big / small end storage format is completely different.

1.3ARM programming model

If   wants to understand that ARM920T is the kernel chip, it can start from several aspects: working mode, ARM exception type, register organization, running status.

  ARM920T is based on the ARM V4T architecture and has seven modes of operation:

The processor describes the normal program execution state of the user mode (usr) ARM processor. Fast interrupt mode (fiq) is used for high-speed data transmission or channel processing. External interrupt mode (irq) is used for normal interrupt handling. Administrative Mode (svc) the protected mode used by the operating system. Data access termination mode (abt) enters this mode when data or instruction prefetching is terminated and can be used for virtual storage and storage protection. System mode (sys) runs privileged operating system tasks. Undefined instruction abort mode (und) enters this mode when undefined instructions are executed and can be used to support software emulation of hardware coprocessors.

The seven working modes of   can be divided into two aspects: privileged mode and non-privileged mode, abnormal mode and non-abnormal mode.

The other six processor modes besides privileged mode and unprivileged mode user mode are called privileged mode (Privileged Modes). In privileged mode, programs can access all system resources and switch processor mode at will, while user mode cannot be switched directly to other modes. Exception mode and non-exception mode, which are also called exception mode (ExceptionModes) except user mode and system mode, are often used to deal with interrupts or exceptions, as well as the need to access protected system resources.

  has different exceptions in exception mode, and the corresponding relationship is as follows:

Exception vector mode reset (Reset) 0x00 management mode undefined instruction (Undefined Instruction) 0x04 undefined instruction abort mode soft interrupt (Software Interrupt) 0x08 management mode instruction prefetch exception (Prefetch Abrot) 0x0C data access termination mode data exception (Data Abort) 0x10 data access termination mode retention (Reserved) 0x14/ interrupt (IRQ) 0x18 data access termination mode fast interrupt (FIQ) 0x1C fast interrupt mode

The   ARM processor has 37 registers, which are divided into several groups (BANK). 31 general registers, including program counters (PC pointer), are 32-bit registers, 6 status registers, 1 CPSR (Current Program Status Register, current program status register) and 5 SPSR (Saved Program Status Register, backup program status register) are used to identify the working status of CPU and the running status of the program, all of which are 32-bit. ARM has seven different processor modes, and there is a corresponding set of register banks in each processor mode.

  register R0~R13 in assembly language is a general register for storing data or address values. They are fully general-purpose registers, are not used by the architecture for special purposes, and can be used for any instruction that uses general registers. These general registers can be divided into the following two categories according to whether they are grouped or not. The ungrouped register (the Unbanked Register) includes R0packet R7, and the packet register (the Banked Register) includes R8~R14.

  ungrouped registers are not used by the system for special purposes, and ungrouped registers can be used in any application where general registers can be used. However, because of its versatility, when the processor mode switch caused by abnormal interrupt, it uses the same physical register, so it is easy to destroy the data in the register.

  packet registers vary depending on how they are used by the processor mode:

Packet registers indicate that each register of the R8~R12 corresponds to two different physical registers. One set is used for all processor modes except FIQ mode, while the other set is dedicated to FIQ mode. Each register of R13 and R14 corresponds to six different physical registers. One of them is common to both user mode and system mode, while the other five are used for five exception modes. Their modes need to be specified when accessing. Name form: R13, R14. It can be one of the following modes: usr, svc, abt, und, irp, and fiq. R13 registers are often used as stack pointers in ARM processors, called SP, and register R14 is also known as connection registers (Link Register,LR).

The   program counter R15 (PC) points to the address being fetched. In exception mode, another register, the Program status backup Register (SPSR), can be accessed. Each exception has its own SPSR, which saves the current value of the CPSR when it enters the exception and restores the CPSR when the exception exits. The bit allocation map of the register is:

Register bits act as N-bit symbol bits. If the result is negative, then N = 1; if the result is positive or 0, then N = 0Z bit if the result of the instruction is 0, then set 1 (usually used to indicate that the result of the comparison is "equal") Otherwise, setting 0C bits represents V bits such as carry and borrowings of the operation. In ARM v5 and later versions with DSP instruction extension, bit [27] is designated to indicate whether the enhanced DAP instruction has overflowed, so it is also called Q flag bit. Similarly, bit [27] in SPSR is also known as the Q flag bit, which is used to save and restore the Q flag bit in the CPSR in the event of an abnormal interrupt. In previous versions of ARM v5 and non-E-series processors of ARM v5, the Q flag bit is not defined and belongs to the bit to be extended. I = 1IRQ is disabled F = 1FIQ is disabled the state control bit of the T-bit processor. T = 0, the processor is in the ARM state (that is, 32-bit ARM instructions are being executed). T = 1, the processor is in the Thumb state (that is, 16-bit Thumb instructions are being executed). The T-bit is valid only on T-series ARM processors, and in non-T-series ARM versions, T-bit will always be 0. M [4 ∶ 0] as the bit mode control bit, its specific control mode is shown in the following table.

The running state of   ARM processor can be divided into two states: ARM and Thumb. The PC value in ARM state is word alignment (4 bytes), and the PC value in Thumb state is half word alignment (2 bytes).

II. The instruction system of ARM

In   embedded development, assembler is often used in very critical places, such as initialization when the system starts, environment preservation and recovery when going in and out of interrupts, functions that are very demanding on performance, and so on. The instruction set of ARM microprocessor can be divided into six categories: jump instruction, data processing instruction, program status register (PSR) processing instruction, load / storage instruction, coprocessor instruction, exception generation instruction.

2.1 Jump instruction

  jump (B) and jump join (BL) instructions are standard ways to change the order in which instructions are executed. ARM generally executes instructions in word address order, using conditional execution to skip certain instructions when needed. As long as the program must be executed out of order, the control flow instruction is used to modify the program counter. There are three main instructions:

Instruction syntax format jump range jump instruction B and jump instruction with connection BLB {L} {} PC+-32MBBX jump instruction with state switch BXBX {} absolute address 4GBXL with state switch connection jump instruction BLXBLX absolute address 4G

2.2 data processing instructions

  should know the addressing mode of ARM before understanding the data processing instructions of ARM. The addressing methods of data processing instructions can be divided into three types: immediate data addressing mode, register addressing mode and register shift addressing mode. Its grammatical format is:

{} {S}, of which there are 11 forms.

Data instruction addressing instruction immediate number in the immediate number addressing instruction is obtained by a 8bit constant moving 4bit even digits. The value of ADD R3 and R3 plus 1

Comparison between the value of CMP R7 and 1000

BIC R9, R8, 0xFF00; clear 15 bits from R8, and save the results in R9.

Register addressing mode the value of the register can be directly used in data operation instructions, this kind of addressing method is often used by all kinds of processors, and it is also a more efficient addressing mode. ADD R4, R3, R2; R2 plus R3, the result is sent to R4.

CMP R7 and R8; compare the values of R7 and R8

The value of the register in the register shift addressing mode can be processed by the barrel shift register before being sent to the ALU. Preprocessing and shift occur in the same cycle, so the effective use of shift registers can increase the efficiency of code execution. MOV R1,R0,LSL # 2

RSB R9,R5,R5,LSL # 1

There are mainly several kinds of memory access instruction addressing methods.

The address code in the register indirect addressing instruction gives a general register number, and the required operands are stored in the storage unit of the address specified in the register, that is, the register is the address pointer of the operands. The Operand is stored in memory. LDR R0, [R1]; R0 ← [R1] (take the value in R1 as the address and save the data in this address in R0) STR R0, [R1] [R1] ← R0 register instruction addressing means addressing adds the contents of the base register to the offset given in the instruction to form an effective address of the operands. Addressing is used to access memory units near the base address, often for table lookups, array operations, functional register access, and so on. LDR R2, [R3 ← 4]; R2 ← [R3 + 4] (add the value in R3 as the address, take out the value of this address and save it in R2) STR R1, [R0Mai Murray 2] [R0-2] ← R1 Multi-register addressing meaning addressing adopts multi-register addressing mode, one instruction can complete the transmission of multiple register values, and this addressing mode can complete the transmission of up to 16 register values with one instruction. LDMIA R0, {R1 ← R2, R3, R5}; R1 ← [R0] (IA means post-increment); R2 ← [R0 + 4] (IB means first increment); R3 ← [R0 + 8] (DA and DB denote later and first decrement) R5 ← [R0 + 12] Multi-register addressing meaning stack addressing stack operation order is divided into "last in, first out" and "first in, first out". Implied in stack addressing, it uses a special register (stack pointer) to point to a storage area (stack), and the storage unit pointed to by the pointer is the top of the stack.

Upward growth: growing to a higher address, called an incremental stack; growing downward: growing to a lower address, called a decreasing stack.

The stack pointer points to the valid data item of the last pressed stack, called Full Stack, and the stack pointer points to the next empty position to be placed, called the empty stack (

Empty Stack).

The way the stack works indicates that the full incremental stack stack pointer points to the last pressed data and is generated from a low address to a high address. Such as instructions LDMFA, STMFA and so on. The full decreasing stack stack pointer points to the last pressed data and is generated from a high address to a low address. Such as instructions LDMFD, STMFD and so on. The null incrementing stack pointer points to the next empty location where the data will be placed and is generated from a low address to a high address. Such as instructions LDMEA, STMEA and so on. The null decrement stack pointer points to the next empty location where the data is to be placed and is generated from a high address to a low address. Such as instructions LDMED, STMED and so on.

  data manipulation instruction refers to the instruction to operate the data stored in the register. It includes data transfer instruction, arithmetic instruction, logic instruction, comparison and test instruction and multiplication instruction. If the S prefix is used after the data processing instruction, the execution result of the instruction will affect the flag bits in the CPSR.

The   ARM multiplication instruction completes the multiplication of two data. The result of multiplying two 32-bit binary numbers is a 64-bit product.

Multiplication instruction description MUL instruction MUL (Multiply) 32-bit multiplication instruction multiplies the values in Rm and Rs, the lowest 32 bits of the result are saved in Rd, the MLA multiplication-accumulation instruction MLA (Multiply Accumulate) 32-bit multiplication-accumulation instruction multiplies the values in Rm and Rs, and then the product is added to the third Operand, and the lowest 32 bits of the result are saved in Rd. The UMULL instruction UMULL (Unsigned Multiply Long) is a 64-bit unsigned multiplication instruction. It multiplies the values in Rm and Rs as unsigned numbers, and the lower 32 bits of the result are saved in RsLo and the higher 32 bits are saved in RdHi. The UMLAL instruction UMLAL (Unsigned Multiply Accumulate Long) is a 64-bit unsigned long multiplication-accumulation instruction. The instruction multiplies the values in Rm and Rs as unsigned numbers, and the 64-bit product is added to RdHi and RdLo. The lower 32 bits of the result are saved in RsLo and the higher 32 bits are saved in RdHi. The SMULL instruction SMULL (Signed Multiply Long) is a 64-bit signed long multiplication instruction. The instruction multiplies the values in Rm and Rs by signed numbers, and the lower 32 bits of the result are saved in RsLo and the higher 32 bits are saved in RdHi. The SMLAL instruction SMLAL (Signed Multiply Accumulate Long) is a 64-bit signed long multiplication-accumulation instruction. The instruction multiplies the values in Rm and Rs by signed numbers, and the 64-bit product is added to RdHi and RdLo. The lower 32 bits of the result are saved in RsLo and the higher 32 bits are saved in RdHi.

2.3 load / store instructions

The   Load/Store memory access instruction transfers data between the ARM register and the memory. There are three basic data transfer instructions in ARM instructions. Single register Load/Store instruction (Single Register); multiple register Load/Store memory access instruction; single register exchange instruction (Single Register Swap).

The instruction specifies that the Load/Store instruction of a single register is used to send a single data into or out of a register. Supported data types are bytes (8 bits), halfword (16 bits), and words (32 bits).

Sample code: LDR R2, [R5]; store the word data of R5 pointing to the address in R2STR R1, [R0 < 0x04]; store the data of R1 to the R0+0x04 address LDRB R3, [R2], #-1 The byte data of R2 pointing to the address is stored in R3, and the R2=R2-1 instruction indicates the Load/Store memory access instruction of multi-registers. the Load/Store memory access instruction of multiple registers is also called bulk load / storage instruction, which can transfer data between a set of registers and a continuous memory unit. LDM is used to load multiple registers, and STM is used to store multiple registers.

Sample code: LDR R0 data instruction; set source data address LDR R1 data; set destination address LDMIA R0, {R2~R9}; load figure 8 data into register R2~R9 STMIA R1, {R2~R9}; store register R2~R9 to destination address instruction description single data exchange instruction is a special case of Load/Store instruction, which exchanges the contents of a register unit with register contents.

2.4 Program status Register (PSR) processing instruction

The   ARM instruction set provides two instructions that directly control the program status register. The MRS instruction is used to pass the value of CPSR or SPSR to a register; MSR, by contrast, passes the contents of a register to CPSR or SPSR. The combination of these two instructions can be used to read / write to CPSR and SPSR.

(1) the syntax format of MRS instruction: MRS {cond} Rd, PSR;Rd is the target register, Rd is not allowed to be program counter (PC). PSR is CPSR or SPSR. Instruction example: MRS R1 cond PSR_field,Rm; read the CPSR status register and save it in R1; read the SPSR status register and save it to R1. (2) the syntax format of the MSR instruction MSR {cond} PSR_field,#immed_8r or MSR {cond} PSR_field,Rm sets the bits to be operated in the status register. The 32-bit status register can be divided into four 8-bit fields (field). Bits [31: 24] is the conditional flag bit field, represented by f; bits [23:16] is the state bit field, represented by s; bits [15: 8] is the extended bit field, represented by x; bits [7: 0] is the control bit field, represented by c Immed_8r specifies the immediate number of fields to be transferred to the status register, 8 bits; Rm specifies the data source register for the field to be transferred to the status register. Instruction example: MSR CPSR_c,#0xD3; CPSR [7:0] = 0xD3, switch to management mode MSR CPSR_cxsf,R3; CPSR=R3

2.5 coprocessor instruction

  ARM coprocessor instructions can be divided into three types: coprocessor data operation, CDP; coprocessor data transfer instructions, including LDC and STC; coprocessor register transfer instructions, including MCR and MRC.

2.6 exception generation instruction

The   ARM instruction set provides two instructions that generate exceptions, through which exceptions can be realized by software.

3. The ARM-THUMB subroutine calls the rule ATPCS

In order to enable C language programs and assemblers to call each other,   must make rules for calls between subroutines. In ARM processors, this rule is called ATPCS: rules for subroutine calls of ARM programs and Thumb programs. The basic ATPCS rules include register usage rules, data stack usage rules and parameter transfer rules.

3.1. Register usage rules

There are 16 registers of r0~r15 in the ARM processor, and their uses have some agreed conventions, and aliases are defined according to these uses, as shown in the following table:

The register alias uses the regular TextTextTextr15pc program counter r14lr connection register r13sp data stack pointer r12p subroutine scratch register r11v8ARM state local variable register 8r10v7, s1ARM state local variable register 7, data stack limit pointer r9v6 for data stack checking in ATPCS, sbARM state local variable register 6, static base address register r8v5ARM state local variable register 5r7v4 in ATPCS supporting RWPI, WrARM state local variable register 4, Thumb state working register r6v3ARM state local variable register 3r5v2ARM state local variable register 2r4v1ARM state local variable register 1r3a4 parameter / result / scratch register 4r2a3 parameter / result / scratch register 3r1a2 parameter / result / scratch register 2r0a1 parameter / result / scratch register 1

3.2. Rules for using data stacks

The   data stack has two growth directions: when it grows in the direction of decreasing memory address, it is called DESCENDING stack; when it grows in the direction of internal address increase, it is called ASCENDING stack.

What   calls the growth of the data stack is moving the stack pointer. When the stack pointer points to the top element of the stack (the last data on the stack), it is called the FULL stack; when the stack pointer points to an empty data unit adjacent to the top element of the stack (the last data on the stack), it is called the EMPTY stack.

  combines these two characteristics, data stacks can be divided into the following four types: ① FD Full Descending, full decline; ② ED Empty Descending, empty decline; ③ FA Full Ascending, full increment; ④ EA Empty Ascending, empty increment.

  ATPCS specifies that the data stack is of type FD, and the operation on the data stack is 8-byte aligned. Use stmdb/ldmia bulk memory access instructions to manipulate the FD data stack.

3.3. Parameter transfer rules

  generally speaking, when the number of parameters does not exceed 4, the four registers of r0~r3 are used to pass parameters; if the number of parameters exceeds 4, the remaining parameters are passed through the data stack. For general returned results, a0~a3 is usually used to pass.

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