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This article mainly introduces how to use the STM32 shadow register, has a certain reference value, interested friends can refer to, I hope you can learn a lot after reading this article, the following let Xiaobian take you to understand.

01. Overview

In the timer block diagram, there is a small detail, and there is a shadow under some registers

These shadows indicate that there are shadow registers in these registers.

There is also a description of the shadow register in the legend:

According to the control bit, after the U event occurs, the contents of the preloaded register are transferred to the valid register. This is the description of the shadow register.

The shaded register (AutoReloadRegister) means that physically this register corresponds to two registers, one is a register that the programmer can write or read, called preloadregister (preload register), and the other is a register that is invisible to the programmer but really plays a role in the operation, called shadowregister (shadow register).

There are three register names.

AutoReloadRegister .

Preloadregister .

Shadowregister .

My understanding here is that the AutoReloadRegister automatic reload register is a concept register, and the definition of each bit can be found in the register table, which consists of the preloadregister preload register and the shadowregister shadow register. We users can access, can modify or read are preloaded registers, ST just open them out (shadow registers are not open to users), it is actually ARR registers.

The benefits of designing preloadregister and shadowregister are:

All the registers (shadowregister) that really need to work can be updated to the contents of the corresponding preloadregister at the same time (when an update event occurs), which ensures that the operations of multiple channels can be accurately synchronized. If there is no shadowregister, or preloadregister and shadowregister are through, that is, when the software updates preloadregister, shadowregister is updated at the same time, because it is impossible for the software to update multiple registers at the same time, resulting in the timing of multiple channels can not be synchronized, if coupled with other factors (such as interruptions), the timing relationship of multiple channels may be unpredictable.

There are three types of shadow registers seen:

1. PSC (Prescaler)

2. ARR (AutoReloadRegister)

3. CCR (Capture/Comparex Register)

4 、 REPRegister

02, PSC (Prescaler)

In the description of the prescaler:

It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as thiscontrol register is buffered. The new prescaler ratio is taken intoaccount at the next update event.

Excerpt from STM32F207 Reference manual manual

Because the control register has a buffering function, the prescaler can be changed in real time. The new pre-division ratio will be used when the next update event occurs.

Counter sequence diagram when frequency division of prescaler is changed from 1 to 2

Here we see that there is a shadow register in the prescaler register, but there is no control bit to control it, and its preload register is connected to the shadow register.

The working mode is as follows:

Note:

In the ST manual, shadow registers are described as buffers, and shadow registers for prescalers are described as registers with buffering functions. Among them

It is also described here that TIMx_ARR registers are not buffered.

03, ARR (AutoReloadRegister)

Control bit:

In the time base unit, it is explained as follows

The content of the preload register are transferred into theshadowregister permanently or at each update event (UEV), depending on theauto-reloadpreload enable bit (ARPE) in TIMx_CR1 register.

Excerpt from STM32F207 Reference manual manual

The contents of the preload register can be transferred either directly to the shadow register or to the shadow register each time an update event (UEV) occurs, depending on the automatic reload enable bit (ARPE) in the TIMx_CR1 register.

That is, the ARPE bit of TIMx_CR1 determines the order of time in which the pre-loaded register data is passed into the shadow register.

Counter sequence diagram, update event on ARPE=0 (TIMx_ARR is not preloaded).

As you can see from the above two figures, if you change the automatic overload register to 0x36 before you reach 0x36, an action will occur when counting to 0x36.

Counter sequence diagram, update event on ARPE=1 (TIMx_ARR preload).

As can be seen from the above two figures, if you change the automatic reload preload register to 0x36 before you reach 0x36, there will be no action when counting to 0x36. At this time, the automatic overload preload register value will be assigned to the automatic reload shadow register.

There are two ways to transfer from the preloaded register ARR to the shadow register, one is to update immediately, and the other is to update after the trigger event; these two ways mainly depend on the "ARPE" bit in register TIMx- > CR1

ARPE=0, when the ARR value is modified, update the shadow register value immediately

ARPE=1, when the ARR value is modified, the value of the shadow register must be updated after the next event UEV occurs

How to immediately change the value of the shadow register instead of the next event; the method is as follows

1. ARPE=0.

TIM_ARRPreloadConfig (ch2_Master_Tim, DISABLE)

2. In ARPE=1.

TIM_ARRPreloadConfig (ch2_Master_Tim, ENABLE)

After we change the preload register, we immediately set the UEV event, that is, to change the UG bit registered by EGR, as follows

TIM1- > ARR = period-1; / / set cycle TIM1- > CCR1 = period > > 1; / / set duty cycle 50% TIM_GenerateEventTIM1,TIM_EventSource_Update); / / active occurrence of UEV event, UG=1

The working mode is as follows:

04, CCR (Capture/Comparex Register)

There is also a text description in counter mode:

The UEV event can be disabled by software by setting the UDIS bit inthe TIMx_CR1 register. This is to avoid updating the shadow registerswhile writing new values in the preload registers .

Excerpt from STM32F207 Reference manual manual

The UDIS location 1 in the TIMx_CR1 register can be disabled by the software to update the event UEV event. This avoids updating the shadow register when a new value is written to the preloaded register.

That is, the UDIS bit in the TIMx_CR1 register indirectly determines whether the pre-loaded register data is passed into the shadow register.

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