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Guide reading

How is a chip born?

How is a CPU designed?

What is the difficulty of designing a CPU?

Guide reading

In recent days, the news all over the moments is that ZTE has been "blocked with one sword" and all chip imports and system software services have been stopped by the United States. For ZTE, which relies on the US for its chips, it is basically in a state of shock, with upstream and downstream production lines shutting down and the future of 80,000 employees uncertain. The impact of the ZTE incident on the IT/IC, and even on ordinary people, is so great that the news of various self-media, official accounts and news APP these days are all related to chips, semiconductors and integrated circuits: what is a chip? How big is the chip gap between China and the United States? All kinds of jokes were born: the same pile of sand, someone made a chip out of it, someone made bricks out of it, and the house price went up in the sky. There is more news, a lot of news is more and more nonsense, and many of them are speechless. Inferiority and arrogance often come from ignorance. Today, I will synthesize the knowledge of the industry and the news on the reference network to give you some knowledge related to integrated circuits. For embedded developers, learning about the field of integrated circuits will also be of great help to their own knowledge system and understanding of the embedded industry.

How is a chip born?

The above joke is right. The raw material of the chip is sand. Today, let's share with you how a pile of sand becomes a chip in our mobile phone.

Chips belong to semiconductors, which are a kind of substance between conductors and insulators. The elements of silicon, germanium and selenium in the periodic table all belong to semiconductors. In addition to these elements, some compounds formed by doping also belong to the category of semiconductors. These compounds are widely used in semiconductor industry, such as gallium arsenide, indium phosphide, silicon carbide, gallium nitride, etc., because of their ability to excite carriers at room temperature and make up for some shortcomings of elemental materials. The concept of integrated circuits has risen sharply in the past few days. I think I want to take advantage of the opportunity to hype graphene again. Graphene does not actually count as a semiconductor. Although it may be achieved by doping, it is currently mainly used as a conductor, such as in rechargeable batteries. Among these semiconductor materials, only silicon is widely used in integrated circuits and acts as the raw material of integrated circuits. In nature, silicon is the second most abundant element, such as sand, which contains a lot of silicon dioxide. Therefore, the raw materials for manufacturing chips are extremely rich and inexhaustible.

How to extract elemental silicon from sand involves a series of chemical reactions. The higher the purity of the extracted silicon is, the higher the quality is. The extracted monocrystalline silicon is made into different sizes according to different needs and processes, such as 6 inch, 8 inch, 12 inch and so on.

Next, cut the silicon rods into slices like cucumbers. Each piece is called a wafer or translated as a crystal element. Crystal element is the carrier of designing integrated circuit, and the circuit we design will be realized on crystal element finally. Hundreds of chip circuits can be realized on each crystal element, as shown in the following figure, each small grid can be regarded as the implementation of a chip circuit. Next, we have to cut, package and lead out the pins of these chip circuits before they can be welded to our development board to make the whole machine products.

So how do you realize the circuit on the crystal element? Take the crystal element under the microscope and you will find that it is full of 3D circuits, like a huge labyrinth:

If we want to understand how to realize the circuit we designed on the crystal element, we need a little basic knowledge of electronic circuit. The circuit is composed of a large number of transistors, diodes, CMOS transistors, capacitors and other components. We understand how a CMOS transistor is realized on the silicon wafer, and also understand the realization principle of the whole circuit on the wafer. The realization principle of these components is actually the realization principle of PN junction. The working principle of PN section is also the basic working principle of semiconductors. PN junction is the basis of diodes, diodes and other semiconductor devices. If you want to understand the conductive principle of the PN section, you also need to know a little about the conductive principle of the metal.

We know that an atom consists of protons, neutrons and extra-nuclear electrons: neutrons are uncharged, protons are positively charged, atoms are negatively charged, and the whole atom is neutral. According to the energy level distribution of electrons, it is most stable when the outermost number of electrons of an atom is 8. For the sodium atom, the distribution of the extra-nuclear electron layer is 2-8-1, and the outermost electron has the largest energy and is less binding by the nucleus, so it is the most unstable, and it is easy to transition from the sodium atom and become a free-moving electron when excited. Under the action of an electric field, these free-moving electrons will move freely to form an electric current, which is the principle of conducting electricity. Many metal elements have less than 4 electrons in the outermost layer, so they are easy to lose electrons, so they are easy to conduct electricity and are conductors. For the chlorine atom, the outermost seven electrons tend to capture one electron, forming a stable structure of the outermost eight electrons. The chlorine atom cannot produce free-moving electrons, so it cannot conduct electricity, so it is an insulator.

Semiconductor elements, generally the outermost four electrons, are special: these atoms often exist through the mode of "sharing electrons". Multiple atoms share their outermost electrons and form a stable structure through covalent bonds.

But stability is not absolute. When these electrons are excited by energy, they also transition into free-moving electrons, leaving the same number of holes in the covalent bond. These free-moving electrons are very few, and under the action of the electric field, they will also move to form an electric current; at the same time, the electrons near the hole can easily jump over to fill the hole, causing the hole to move, and the hole is positively charged. The movement of the hole will also form an electric current.

Therefore, semiconductor conduction has two kinds of carriers: free electrons and holes. But because of the nature of silicon, only a few free electrons and holes are generated, which determines that semiconductors cannot conduct electricity like metals, but not at all like insulators. However, it is this characteristic that has contributed to the rapid development of semiconductors.

Since the concentration of free electrons and holes in semiconductors is very small and the conductivity is weak, can we find a way to increase the concentration of the two kinds of carriers? When the concentration goes up, won't the electrical conductivity be enhanced? There is a way, and that is to mix it. We can add two different elements on both sides of a semiconductor: trivalent elements such as boron and aluminum on the other. The distribution of electrons in boron is 2-3, and there are three electrons in the outermost layer of boron. When it forms a covalent bond with the four electrons in the outermost layer of silicon, it lacks one electron, so it seizes an electron from the adjacent silicon atom, thus creating a hole. This doped semiconductor is called hole semiconductor, or P-type semiconductor for short.

We adulterate some pentavalent elements on the other side of the semiconductor, such as phosphorus. The outermost layer of the phosphorus atom has five electrons. when it forms a covalent bond with the four electrons in the outermost layer of the silicon atom, one more electron becomes a free-moving electron. This kind of semiconductor is called electronic semiconductor, or N-type semiconductor for short.

We mix different elements on both sides of a conductor to make it into different semiconductors, P-type on one side and N-type on the other.

At the intersection of the two, a special interface is formed, called the PN junction. Once you understand the PN junction, you will understand the core principles of semiconductors. Let's take a look at what's going on in the PN junction.

First of all, due to the different concentrations of holes and free electrons on both sides of a semiconductor, mutual diffusion occurs at the boundary. After crossing the boundary, the holes and free electrons diffused into the other region neutralize each other at the boundary, and after the holes at the boundary of the P region are neutralized by the diffused free electrons, the remaining negative ions are all negative ions that cannot move freely; similarly, the positive and negative ions are left at the boundary of the N region, and these positive and negative ions can not move, forming the space charge region and depletion layer. At the same time, a built-in electric field will be formed in this area. This built-in electric field prevents the hole in the P region from continuing to spread to the N region, and prevents the free electrons from the N region from diffusing to the P region, thus reaching a balance between the diffusion of many carriers and the drift of minority carriers. This area is what we call the PN knot. The movement of the carrier has now reached equilibrium, so the current flowing through the PN junction is also zero.

This PN section looks fine, but it has one feature: unidirectional conductivity. It is this characteristic that has established its cattle status and formed the foundation of the entire semiconductor building. Let's first see how this characteristic is realized: when we add a positive voltage at both ends of the PN junction, the P region is connected to the positive electrode, which weakens the built-in electric field of the PN junction, destroys the balance, and the holes and free electrons spread to both sides to form a current, showing conductive properties. When we add the reverse voltage, the built-in electric field is enhanced, which prevents the carrier from spreading and does not form a current, so it shows the characteristic of high resistance and does not conduct electricity.

No matter diodes, transistors or MOSFET FETs, their internals are all based on the principle of PN junctions. We understand the principle of PN junctions, and then let's look at how to realize PN junctions on a crystal element:

This involves all aspects of integrated circuit technology, including lithography, etching, ion implantation, thin film precipitation and other steps. In order to simplify the process and make it easy to understand, let's talk about the two core steps, lithography and ion implantation. Ion implantation is doping. According to the previous understanding, silicon is doped with trivalent element boron and pentavalent element phosphorus to form various components and circuits with PN structure. Lithography is to dig various doping windows on the crystal element for the subsequent ion implantation operation.

The principle is very simple, but if we want to achieve tens of millions of gates of circuits and hundreds of millions of transistors on a silicon substrate, it will be more difficult. Especially for nanoscale circuits, such as 28nm and 14nm, ten million gate transistors are engraved on a small crystal element, which requires that the size of each component should be very small. At this time, the lithography machine is on the scene, and the lithography machine is mainly used to map the ten million gate level circuits you designed to the crystal element. The requirement for lithography machine is very high, it should be very precise. So the lithography machine is very expensive, the most powerful is the Dutch lithography giant ASML, which is hot online recently, a lithography machine costs 100 million euros, and many contract manufacturing giants such as TSMC, Samsung and Intel are its customers.

The function of the lithography machine is to dig a variety of doping windows according to the mask, and then generate PN nodes by ion implantation to build tens of thousands of components. The components in the circuit are made up of countless PN structures through this complex process. At the same time, ion implantation is also a great knowledge. PO a formula about ion implantation on the Internet. Feel its charm:

After these processes are completed, there will be hundreds of chip prototypes on a single chip: chip circuits, which in technical terms are called Die.

Then it has to be cut, encapsulated, pins and tested before it becomes the look of the chip we see on the market.

How is a CPU designed?

In the previous section, we learned about the manufacturing process of the chip, that is, how to extract silicon from the sand, cut the silicon into slices, realize PN junctions on the chip by ion implantation, and realize all kinds of diodes, transistors and CMOS transistors, thus realizing the approximate flow of 10 million gate LSI. Next, let's take a look at how a CPU is designed. Integrated circuit design is generally divided into analog IC design, digital IC design and digital-analog hybrid design. The basic flow of digital IC design, such as designing an ARM Soc CPU chip, is as follows:

1) Design chip specifications: according to the requirements, design the basic framework, function and module division. Some complex chips may also need to be modeled and simulated using tools such as MATLAB.

2) HDL code implementation: the hardware function to be realized by VHDL or Verilog language is described, simulated and modified continuously by EDA tool, and verified until the logic function is completely correct. This kind of simulation is generally called pre-imitation, which only verifies whether the logic function is correct and does not consider the delay. This stage is also the most important stage, which generally takes a lot of time and verification engineers to constantly verify the correctness of the chip function. Sometimes in order to improve efficiency, hardware simulation is used to verify through the FPGA platform. Of course, this is also the job of digital IC verification engineers.

3) Logic synthesis: after the simulation verification, a special EDA tool is used to convert the HDL code into a logic gate circuit. The technical term is to translate HDL code into a gate-level netlist. In the process of synthesis, some constraints need to be set to make the synthesized circuit meet the requirements in terms of area, timing and other parameters. The simulation at this stage is generally called post-imitation, and the delay and other factors should be taken into account, which is very close to the actual chip.

Netlist files are used to describe the connections between components in a circuit. Students who have the foundation of digital circuits may know that any logical relationship or operation can be transformed into the corresponding gate-level circuit. The Netlist is used to describe the connection information of these gate-level implementation circuits.

It is also important to note that gate-level circuits are provided by different wafer factories, that is, chip foundry, in the form of process libraries, such as SMIC, TSMC and so on. If the chip you design is to be manufactured by TSMC, and the process requirement is 28nm, then when you design the chip, TSMC will provide you with a 28nm-level process library, and the circuit parameters generated by your synthesis are consistent with the process parameters used in TSMC's chip production.

4) Simulation verification: all kinds of static timing analysis and verification are carried out on the generated gate-level circuit. After passing, the whole front-end design is over: from the RTL code to the generation of gate-level Netlist circuit.

5) back-end design

Through the front-end design, we have generated the gate-level Netlist circuit, but this is still a long way from the actual chip circuit, we still need to constantly improve and optimize it, and further design into a physical layout, that is, the layout needed by the foundry to make a mask. Back-end design consists of many steps, generally including:

DFT:designed for test, design for testability. The chip often has its own test circuit, and the scan chain is inserted in the design.

Layout planning: placement position of each IP module circuit, clock line synthesis, routing of ordinary signal lines

Physical verification of layout: check of design rules, connection width, spacing in line with process requirements, simple rules of electrical rules, and so on.

After the physical layout verifies the ok, the physical layout is handed over to the chip foundry (foundry) in GDSII file format. At this point, the whole chip design simulation verification process ends, which we call tap-out.

The physical layout is a series of geometric figures transformed from the circuits we designed, such as the image above, which is similar to the PCB layout and is also divided into many layers. The physical layout includes the size of the integrated circuit, the topological relationship of each layer and so on. The foundry will make masks based on this information, and then use lithography machines to cut out doping windows on the silicon wafer substrate through these masks, and then carry out ion implantation into the silicon wafers, doping different trivalent and pentavalent elements to form PN, and then form a variety of components and circuits. Through etching and other processes, a multi-layer three-dimensional 3D circuit structure can be generated on the wafer.

All right, at this point, we have explained the general process of chip design and manufacturing to you. It looks very simple. In fact, every step of integrated circuit design and manufacturing has a very high technical content. The integrated circuit industry is a highly professional industry, each link is guarded by different industry giants, from chip design, manufacturing, various EDA tools, IP cores, lithography machines, etching machines. Each link has very professional manufacturers, service providers, EDA tool vendors, precise and rigorous cooperation, but also share the excess profits on the IC design industry chain.

How hard is it to design a CPU?

Many online media even use tables to list the dependence rate and self-sufficiency rate of Chinese chips, which is 0% in many areas except AP, an application processor in the consumer electronics field. This also shows from one point of view: the space for the development of our integrated circuits is huge and imaginable.

Places with relatively large gaps are mainly in the fields of simulation, radio frequency, AD conversion, and so on, which are basically monopolized by some giants in Europe and the United States. What is even more sad is that many core areas have now banned Chinese from engaging in this field of work. This shows that the US Government attaches great importance to technical protection in these sophisticated areas. In some areas of consumer electronics, due to the IP authorization model of ARM, which greatly reduces the design threshold of SOC, coupled with the mature and strict division of labor system of the semiconductor industry: design, OEM, packaging and testing, China has developed rapidly in the field of consumer electronics SOC design in recent years, and many chips and companies have emerged, such as Hayes, Spreadtrum, Lianxin, Quanzhi, Ruixin Micro and so on. From the mobile phone baseband, RF to AP have gradually narrowed the gap with the international semiconductor giants. For example, Hayes's Kirin series is already comparable to the Snapdragon series of Standard Qualcomm.

Under the ecological and business model built by ARM, SOC chip design companies can have the opportunity to compete with these chip giants, or at least participate: you Niu X, you can get the instruction set authorization of ARM to do your own micro-architecture. I don't have the strength to build a building block in a low-end field. The embedded market, unlike PC X86, is decentralized, multi-demand and difficult to monopolize. So this gives many ARM AP chip companies a lot of opportunities, you make mobile phones, I do tablets, smart TVs, network boxes, game consoles, mining machines, as long as you find the right direction, with the advantage of low cost, you can survive, and then map the technology to slowly accumulate and develop. So in the ARM AP area, you will see a lot of companies, and there will be a lot of companies in the future, which should be able to meet the chip self-sufficiency as soon as possible, and of course, it also provides a lot of jobs for embedded developers.

In PC and servers, it may not be so easy to break through. We know that in the field of X86, it is the world of Intel and AMD. Is it difficult to design a chip with X86 architecture? In fact, it is not difficult, domestic can find a lot of companies can design it. So what's the hard part? It's ecological and patent licensing. Intel can be said to be the dominant company in the X86 field. Under its patent protection, it basically blocks the way that you want to design your own X86 architecture CPU. No matter how much money you have, you will not be allowed to do it or grant you a patent license. AMD is still the United States in order to prevent monopoly, to promote Intel and its patent cross-licensing, to achieve a balance, but AMD does not seem to have an easy life, in the CPU area is also difficult to be pressed by Intel. In addition, there is another company, Taiwan's via Electronics: VIA, which displays the VIA logo as soon as the computer is turned on. VIA also has some X86 patents and has been granted Intel patents, but it seems to be very difficult to do CPU, and its profits in chips are not as profitable as its hotel business. In fact, there is no way, the winner takes all, and the rest may not even be able to drink soup. Looking at the news on the Internet, it seems that Zhaoxin was established as a joint venture with Shanghai state-owned assets to study X86 CPU and graphics cards. The country has spent a lot of money. I don't know if I can wade out a way.

With the target of the domestic chip company, there is a more famous: Godson. Godson takes the MIPS route. Like ARM and X86, MIPS is also a kind of instruction set, and it is also a living instruction set in the world. It can be said to be a tripartite struggle with ARM and X86. It is said that 5 million of Godson got the permanent license of the MIPS instruction set, and then constantly added and improved the instruction set to form its own instruction set. The advantage of Godson is that MIPS has a certain ecological market, so it is not necessary to build its own ecology from scratch, which is conducive to the promotion of its own CPU. According to the relevant information on the Internet, the newly developed micro-architecture GS464E has surpassed the i3 architecture of Intel and has a slight gap with i5, but at the same time it has surpassed the low-power architecture of the same period, such as Intel Atom, VIA Nano, ARM Cortex-A57, etc.

Here we need to popularize what is the instruction set and micro-architecture. Instruction set, if you have studied assembly language, you may know some assembly instructions. These assembly instructions are actually mnemonics of the instruction set. When we design a CPU architecture, we must design a series of instructions. These instruction sets can be regarded as a standard. When we design CPU hardware circuits based on these instruction sets, we design some instruction decoding and execution circuits to execute our instruction set. Then the CPU hardware circuit designed according to the instruction set is the microarchitecture. Different CPU architectures have different instruction sets, which leads to different compilation and development environments for different CPU architectures. For example, in the ARM architecture, we need to develop a compiler that translates our C language programs into the instruction set of ARM before running on the CPU of the ARM architecture. For the X86 platform, we need to develop another compiler to translate the C language program into X86 instructions before it can run on the X86 platform. Why can't ARM instructions be run on the X86 platform? Very simple, because the CPU hardware circuit is designed according to the X86 instruction set, only supports the operation of X86 instructions, does not support ARM instructions, can not run.

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