Shulou(Shulou.com)06/02 Report--

Recently, as the job I found was partial to the embedded direction, I began to learn again the knowledge that had been abandoned for two years. Novice learning knowledge feels that there is a common problem: he likes to collect all kinds of videos and materials, and he collects a lot of them in the online disk, but he has never opened it. In the end, he is still a rookie. He has only heard a few concepts, but in fact he does not know what to say. This is the so-called "learning syndrome". And I am also one of them. Recently, learning from the bitter experience, I am ready to settle down to study according to a set of data, and no longer enter the army of data collection. There are a lot of embedded videos or materials on the market, such as Guojie, Wei Dongshan, Huaqing Vision, Zhu Youpeng, etc., each has its own advantages, but in the end, it is the same goal. In my opinion, it is an introduction to eat one of them thoroughly. After that, the growth still depends on the precipitation in the work, look at the source code, and do the project in order to improve.

Now I am going to write about my learning experience according to teacher Wei Dongshan's video. This time it is mainly about how to read the schematic diagram, which is mainly divided into the following parts: GPIO and gate circuit, protocol class interface (UART/I2C/SPI/NAND), memory class interface.

1. Schematic diagram of GPIO and gate circuit

General Purpose Input Output (Universal input / output) is abbreviated as GPIO, or bus extender. In general, GPIO registers can be divided into three categories:

Control register: for input, output, or other special functions

Data register: 1 or 0

Pull-up register: sets whether the IO output mode is high resistance, with pull-up level output, or without pull-up level output

As shown in the figure above, keys can be configured so that the corresponding pin control register is the input function and the LED pin is the output function, so the LED lamp can be turned on or off by pressing the key. Pull-up (pull-down) resistors clamp uncertain signals through a resistor at high (low) levels, and the resistors also limit the current.

The resistor shown above corresponds to the pull-up resistance and the pull-down resistance, respectively. The pin output high level, but due to the influence of the subsequent circuit, the output high level is not high, but can not reach the VCC, affecting the circuit work, so it is necessary to connect the pull resistor. On the contrary, the pull-down resistance allows the chip pin to output a low level, and as a result, the low level of the output affected by the subsequent circuit can not reach the GND, so the pull-down resistance is connected.

A unit circuit used to realize basic logic operations and compound logic operations. The commonly used gate circuits have several logical functions, such as and gate, or gate, non-gate, and non-gate, and or non-gate, XOR gate and so on. As shown in the following figure:

II. Protocol interface

The protocol interface circuit is divided into two aspects: the construction of the hardware circuit and the timing of the pin work. The protocol interface is mainly used to communicate between two devices. Comparing the conversation between two people, there are two problems to be solved:

1. What you say should be understood by others (the same signal protocol is agreed between the two devices)

2. Both sides should not speak too fast, or others will not respond (both sides meet the same timing requirements)

UART

Here, the hardware schematic diagram and timing diagram of the protocol class interface are explained by four communication protocols: UART, I2C, SPI and NAND Flash. The Universal Asynchronous Transceiver (Universal Asynchronous Receiver/Transmitter), commonly known as UART, is an asynchronous transceiver that is part of computer hardware. The data to be transmitted is converted between serial communication and parallel communication. The serial port circuit in TQ2440 is as follows:

Because of the UART transmission process, in order to ensure the validity and transmission distance of the signal, the negative logic level is used, that is, the logic "1" is represented by-3cm color 12V, and the logic "0" is represented by 3cm 12V, so the output signal of 2440 needs voltage conversion. The figure above is the schematic diagram of voltage conversion. In the UART protocol, there is no uniform clock, depending on the start bit and stop bit to identify a frame of data. The frame format starts at 1 bit (low level), data bits 5-8 bits, check bits 0-1 bits, and stop bits (1, 1.5, 2 high-level representations).

I2C

I2C bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips Company. It only needs two wires to transmit information between devices connected to the bus. SDA (serial data line) and SCL (serial clock line) are both bi-directional I / O lines, and the interface circuit is open-drain output. It is necessary to connect the power supply VCC through pull-up resistors. When the bus is idle, both lines are high-level, the external devices connecting the bus are CMOS devices, and the output stage is also an open-drain circuit.

On the I2C bus, each byte sent to the SDA line must be 8 bits, and there is no limit to the number of bytes that can be sent per transfer. Each byte must be followed by a response bit. The first thing to transmit is the highest bit of data (MSB). If the slave has to complete some other functions (such as an internal interrupt service program) before receiving or sending the next complete data byte, the clock line SCL can be kept low, forcing the host to enter a waiting state. When the slave is ready to receive the next data byte and release the clock line SCL, the data transmission continues. The starting condition of data transmission is that the clock keeps high level and the data changes from high level to low level; the end condition is that the clock keeps high level and the data changes from low level to high level.

The data transmission format is as follows:

SPI

SPI is the abbreviation of Serial Peripheral Interface (Serial Peripheral Interface). SPI is a high-speed, full-duplex, synchronous communication bus, and occupies only four lines on the pins of the chip, saving the pins of the chip, while saving space and providing convenience for the layout of PCB. It is precisely because of this easy-to-use feature that more and more chips integrate this communication protocol, such as AT91RM9200. In TQ2440, there is no peripheral interface that specifically leads to the SPI bus, but if you look at the 2440 chip manual, you can see that the chip supports the SPI working mode in 4. The bus composition can be shown in the following figure:

The meaning of each pin is: 1) MOSI-Master data output, Slave data input 2) MISO-Master data input, Slave data output 3) SCK-clock signal, 4) / CS-Slave enable signal generated by Master, controlled by Master.

The slave device enable signal and clock signal generated by the SPI interface under the control of Master, the two bidirectional shift registers transmit data by bit to exchange data, and the data is transmitted in front of the high bit and low in the back (MSB first). As shown in the figure above, the data changes on the falling edge of the SCK, and one bit of the rising edge data is stored in the shift register.

NAND Flash

Nand-flash memory is a kind of flash memory, NAND structure can provide very high cell density, can achieve high storage density, and the speed of writing and erasing is very fast. The picture below is a NAND Flash chip. Apart from not using pins and power pins, there are mainly data pins, chip selection, write, read and other pins. A pin function can be found in the chip manual.

In the Nand Flash chip, a chip is called a device, a device can be divided into multiple Block, a Block can be divided into multiple pages, so to read the data of a specified area, it is necessary to transmit the address multiple times.

Four protocol class interfaces are introduced above, and their specific use and programming will be summarized later.

III. Memory class interface

Memory interfaces mainly include SDRAM, NOR Flash and other chips. The signal transmission of these chips can be divided into three categories: chip selection, address signal and data signal. For the access of this kind of device, the chip selection signal is selected first, and then the address is determined before reading the data. In 2440, the memory control is divided into 8 regions, each of which is 128m. The following picture shows the circuit diagram of sdram in TQ2440, which is composed of two 16-bit SDROM to form a 32-bit SDROM. From the diagram, we can know that the chip selection signal is connected to the nGCS6 of 2440. In the memory map of 2440, the starting address of nGCS6 is 0x30000000, which is why when we first started to learn ARM bare metal programming, the teacher asked us to burn the program to 0x30000000. In the figure, the address line is connected to the ADD2-ADD14 of 2440, but not to ADD1 or ADD0. That is because the word width of 2440 is 32 bits, or 4 bytes, and the minimum unit for reading and writing data is 4 bytes. In that case, if you want to process a byte of data, you can only take out 4 bytes, and then remove the required data from it. The data processed must be an integral multiple of 4, so the lowest two-digit address lines can not be connected.

Memory address mapping map in 2440.

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