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This article mainly shows you the "sample analysis of STM32 watchdog", which is easy to understand and well-organized. I hope it can help you solve your doubts. Let the editor lead you to study and study the "sample analysis of STM32 watchdog".

1. Brief introduction of IWDG1.1 independent watchdog

IWDG (Independent watchdog) independent watchdog, which can be used to detect and resolve faults caused by software errors. When the counter reaches a given timeout value, it will trigger an interrupt or generate a system reset.

The independent watchdog's clock is its dedicated low-speed clock (LSI), so it can keep working when there is something wrong with the master clock. Window watchdog clock is obtained by APB1 clock frequency division, through a configurable time window to detect abnormal late or premature operation of the application.

IWDG is most suitable for situations where watchdogs are needed as a watchdog outside the main program, can work completely independently, and require low time accuracy. WWDG is best suited for applications that require watchdogs to function in precise timing windows.

1.2 characteristics of independent watchdogs

① freely runs decrement counter

The ② clock comes from a stand-alone RC oscillator (can operate in standby and stop modes)

③ when the downward counter value reaches 0, a reset occurs (if the watchdog has been activated)

1.3 functional description of independent watchdog

The red box above shows that the watchdog function is powered by the VDD voltage domain, so it still works in stop mode and standby mode.

Write 0XCCCC to the keyword register (IWDG_KR), the independent watchdog starts, and the counter begins to drop from the reset value 0XFFF. When the counter value reaches 0, a reset signal is generated (independent watchdog reset)

Whenever the value of 0XAAAMagi WDGchains RLR is written to the keyword register, it will be reloaded into the counter to avoid the watchdog reset.

1.4 hardware watchdog

If the "hardware watchdog" function is enabled through the device option bit, the watchdog will be enabled automatically when powered on; if the software does not write the corresponding value to the keyword register before the end of the counter count, the system will produce a reset.

1.5 Register access protection

IWDG_PR and IWDG_RLR registers have write access protection. To modify the register, you must first write the code 0x5555 to the IWDG_KR register. Writing other values destroys the sequence, making register access protection effective again. This means that the reload operation (that is, write 0xAAAA) also initiates write protection.

The status register indicates whether the pre-division value and the decreasing counter are being updated.

1.6 Debug mode

When the microcontroller enters debug mode (Cortex ™- M3 kernel stops), the IWDG counter will choose to continue to work or stop working according to the DBG_IWDG_STOP configuration bit in the DBG module

The following figure shows the minimum and maximum values of the IWDG timeout period of LSI under different frequency division conditions.

2. Introduction to WWDG2.1

Window watchdog (Window watchdog) is usually used to monitor software failures caused by external interference or unforeseen logic conditions that cause applications to deviate from the normal running sequence. Unless the value of the decrement counter is refreshed before the T6 bit becomes zero, the watchdog circuit produces a MCU reset when it reaches a preset time period. A MCU reset also occurs if the 7-bit decrement counter value in the control register is refreshed before the decrement counter reaches the window register value. This means that the counter must be refreshed within a limited time window

2.2 main characteristics of window watchdog

① programmable free down counter

② reset condition, when the watchdog is activated, reset when the decrement counter value is less than 0x40; reset when the decrement counter is reloaded outside the window.

③ early Wake up interrupt (EWI): triggered when the decrement counter is equal to 0x40 (if enabled and watchdog activated)

2.3 function description of window watchdog

If the window watchdog starts (WDGA position 1 of the WWDG_CR register), the 7-bit down counter scrolls from 0X40 to 0x3F (T6 has been cleared), resulting in a reset. If the software overloads the counter, a reset occurs when the counter value is greater than the value stored in the window.

The application must write the WWDG_CR register to organize the MCU reset during normal operation. This must occur when the counter value is less than the window register value. The window register value is stored in the WWDG_CR register and must be between 0XFF and 0XC0.

Enable window watchdog

After a reset, window registers are often disabled. Enabling by setting the WDGA bit of the WWDG_CR register cannot be disabled except by reset.

Control down counter

The decrement counter is free to run: the decrement counter continues to decrement the count even if the watchdog is disabled. When enabling a watchdog, position 1 of T6 must be set to prevent immediate reset

The T [5:0] bit contains the number of times before the watchdog produces a reset; the delay time before the reset varies between a minimum and a maximum, because the pre-division value is unknown when writing to the WWDG_CR register. The configuration register (WWDG_CFR) contains the upper limit of the window: to prevent a reset, it must be overloaded when the value of the decrement counter is lower than the window register value and greater than the 0x3F

Note: T6 bit can be used to generate software reset (WDGA position 1 and T6 bit zero)

Watchdog interrupt advanced features

If a specific security operation or data record must be performed before an actual reset is generated, an early wake-up interrupt (EWI) may be used. Enable EWI interrupts by setting the EWI bit in the WWDG_CFR register. When the value of the decrement counter is 0x40, an EWI interrupt is generated. Before resetting the device, a corresponding interrupt service program (ISR) can be used to trigger a specific operation (such as communication or data recording).

In some applications, EWI interrupts can be used to manage software system checks and / or system recovery / functional degradation without generating WWDG resets. In this case, the corresponding interrupt service program (ISR) can be used to overload the WWDG counter to avoid WWDG reset, and then trigger the desired action.

Clear the EWI interrupt by writing 0 to the EWIF bit in the WWDG_SR register

2.4 how to set watchdog timeout

Example: the frequency of APB1 is 24MHz, the frequency is WDGTB [1:0], the setting is 3, and T [5:0] is set to 63.

T = 1x 24000 "4096" 2 "2" 2 * (63) = 24.85ms

About the minimum and maximum values of TWWDG

2.5 Debug mode

When the microcontroller enters debug mode (Cortex ™- M3 kernel stops), the WWDG counter will choose to continue working or stop working according to the DBG_WWDG_STOP configuration bit in the DBG module.

3. Difference

Different application scenarios

IWDG is most suitable for situations where watchdogs are needed as a watchdog outside the main program, can work completely independently, and require low time accuracy.

WWDG is best suited for applications that require watchdogs to function in precise timing windows.

Why do you need a window watchdog?

For the general watchdog, the program can refresh the watchdog at any time before it is reset, but there is a hidden danger. It is possible that the program runs out of order and then runs back to the normal place, or the chaotic program just performs the refresh watchdog operation. In this case, the average watchdog cannot detect it.

If you use a window watchdog, the programmer can set a time window to refresh the watchdog according to the normal execution time of the program, ensuring that the watchdog will not be refreshed in advance and will not lag to refresh the watchdog. In this way, you can detect that the program did not follow the normal path and abnormally skipped some program segments.

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