Shulou(Shulou.com)06/02 Report--

Star memory provides a new generation of high-performance, high-density, low-power and low-cost memory products for the electronics industry. Focus on XRAM product development and design, provide low-latency, low-power and refresh-free dynamic random access memory products are committed to the process of commercialization and industrialization of innovative storage technology to drive the underlying technology of domestic memory chips and related scientific research work, so as to promote the reform and further development of the front-end industry of national memory chip design. Next, Xingyi agent Yingshang Microelectronics introduces how the STM32F4 development board STM32F4 drives the external SRAM chip XM8A51216.

STM32F407ZGT6 comes with a 192-kilobyte SRAM, which is enough for general applications, but in some situations where memory requirements are high, STM32F4's native memory is not enough. For example, running algorithms or running GUI may not be enough, so the STM32F4 development board contains a 1m byte capacity SRAM chip, XM8A51216, to meet the needs of large memory use. We will use STM32F4 to drive XM8A51216 and implement access control to XM8A51216.

Introduction to XM8A51216

XM8A51216 is a 16-bit wide 512K (512K) CMOS static memory chip produced by Xingyi Storage Technology Co., Ltd. The chip has the following characteristics:

⚫ Highway. Has the highest access speed 10/12ns.

⚫ low power consumption.

⚫ TTL levels are compatible.

⚫ fully static operation. No refresh and clock circuits are required.

⚫ tri-state output.

⚫ byte control function. High / low byte control is supported.

The functional block diagram of XM8A51216 is shown in figure 1:

Fig. 1 functional block diagram of XM8A51216

In the figure, A0room18 is the address line, with a total of 19 address lines (that is, 2 ^ 19 = 512K ~ 1K ~ 1024); DQ0~15 is the data line, with a total of 16 data lines. CEn is the chip enable signal, low-level effective; OEn is the output enable signal, low-level effective; WEn is the write enable signal, low-level effective; BLEn and BHEn are high-byte control and low-byte control signals respectively; STM32F4 development board uses XM8A51216 chip encapsulated by TSOP44, which is directly connected to the FSMC of STM32F4, and the XM8A51216 schematic diagram is shown in figure 2:

Fig. 2 XM8A51216 schematic diagram

As can be seen from the schematic diagram, the connection between XM8A51216 and STM32F4:

A [0:18] followed by FMSC_A [0:18] (but out of order)

D [0:15] and FSMC_D [0:15]

UB to FSMC_NBL1

LB to FSMC_NBL0

OE to FSMC_OE

WE to FSMC_WE

CS to FSMC_NE3

The above connection relationship, A [0:18] of XM8A51216, does not connect sequentially to the FMSC_A of STM32F4 [0:18], but this does not affect our normal use of external SRAM, because the address is unique. So as long as the address line is not confused with the data line, the external SRAM can be used normally. The advantage of this design is that it is convenient for our PCB wiring.

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