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We mentioned in the previous section that makefile is essentially a script that is used to interpret and execute. Then its meaning is to define the dependencies between source files and explain how to compile each source file and generate executable files. Let's look at the definition of dependency, as follows

Let's analyze the meaning of the elements in makefile: a > targets: usually the name of the target file that needs to be generated, the name of the command that make needs to execute; b > perequisities: other targets or files on which the current target depends; c > command: the command that needs to be executed to accomplish the goal. Let's talk about the notes in the rules: a > targets can contain multiple targets and use spaces to separate multiple target names; b > perequisities can contain multiple dependencies and use spaces to separate multiple dependencies; c > [Tab] key'\ tdependency, each command line must start with the [Tab] character, and the [Tab] character tells make that this line is a command line. D > continuation character\, you can write the content separately to the next line to improve the readability of the code.

Let's take a look at an example of makefile dependency, as follows

The dependency rule is: a > when the file corresponding to the target does not exist, execute the corresponding command; b > when the dependency is newer than the target in time, execute the corresponding command; c > when the dependency occurs continuously, compare each target on the dependency chain. A little trick here: in makefile, you can add the @ character before the command to make the command have no echo.

Let's take the code as an example to analyze and illustrate.

All: test @ echo "make all" test: @ echo "make test"

The target all we define depends on test, while the test target has no dependency, just executes the print statement. When the test target is executed correctly, the execution statement of the all target will output normally. That is, print the make test first, and then output the make all. Let's take a look at the compilation results.

So why print out only these two sentences, not the echo "make all" we saw in the previous section? The reason is that the @ no echo symbol we added in front of them, let's remove the @ symbol to see the compilation effect.

In the future, if we don't want to see the echo command itself, we can add the @ no echo symbol. Let's take a look at a compilation case of make, which is structured as follows

Let's write the corresponding makefile program according to the above structure and see the execution effect.

Func.c source code

# include int foo () {printf ("void foo ()\ n");}

Main.c source code

Extern void foo (); int main () {foo (); return 0;}

Makefile source code

Hello.out: func.o main.o gcc-o hello.out func.o main.ofunc.o: func.c gcc-ofunc.o-c func.cmain.o: main.c gcc-o main.o-c main.c

Let's take a look at the compilation results.

We see that it has come true. Let's add hello before the statement printed in func.c, and then take a look at the compilation result.

We see that when compiling again, it only compiles the func.c file, not the main.c file, which greatly improves the efficiency of embedded compilation. So here's a tip: in engineering development, you can target both the final executable file name and the all as the first rule in makefile, as follows

Let's compile again and look at the compilation result.

We see that it says that hello.out is up-to-date and the result of the implementation is the same as before. So this tip can greatly improve our inefficiency caused by repeated compilation. We can also compile it again by directly make all, as follows

This time, because the source file has not changed, only the statements following the hello.out target are executed. Improve the learning of the makefile structure, summarized as follows: 1, makefile is used to define the dependency between source files; 2, makefile explains how to compile each source file and generate executable files; 3, there is a continuous dependency between targets in makefile; 4, the dependency exists and the successful execution of the command is a necessary and sufficient condition for the completion of the goal.

Welcome to learn makefile language, you can add me QQ:243343083.

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