Shulou(Shulou.com)06/03 Report--

1. Overview of EDMA3

The core processor based on C66x mainly has two kinds of DMA transmissions: IDMA and EDMA3.

IDMA: only data mobility services within the core (L1P, L1D, L2, CFG) are provided.

EDMA3: data transfer (such as DDR3, MSM SRAM, L2) between two memory-mapped slave terminals (Slave Endpoint) on the device.

The EDMA3 controller is set by the user to serve data transfer from terminals mapped by two memories on the device; to serve software-driven page transfers (for example, between external memory and internal memory), to perform decomposition or subframe fetching of multiple data structures, to serve event-driven peripherals, and to reduce device CPU data transmission tasks.

2. EDMA3 Analysis of the composition of 2.1 EDMA3

In the C6678 processor, IDMA has two channels, EDMA has three channel controllers (CC0, CC1, CC2) and 10 transmission controllers (CC0TC0, CC0TC1,CC1TC0, CC1TC1, CC1TC2, CC1TC3,CC2TC0, CC2TC1, CC2TC2, CC2TC3).

As shown in figure 2-1, CC0 has 16 DMA channels, 8 QDMA channels, 16 interrupt channels, 2 event queues, 2 transmission control TC;CC1 has 64 DMA channels, 8 QDMA channels, 64 interrupt channels, 4 event queues, 4 transmission control TC;CC2 has 64 DMA channels, 8 QDMA channels, 64 interrupt channels, 4 event queues, and 4 transmission control TC.

Figure 2-1 EDMA3 CC resource map

The resources for each TC are shown in figure 2-2.

Figure 2-2 EDMA3 TC resource diagram

2.2 functional usage

CC0 is optimized for data transfer between internal MSMC (Multicore Shared Memory Controller) and DDR3 subsystems, and CC1 and CC2 are used as system peripherals and other transmissions such as moving data between system memories.

There are two channel types for each CC: DMA channel and QDMA channel. Each channel is associated with a given event queue, transport controller, and a given set of PaRAM parameters.

The main difference between DMA channels and QDMA channels is how the transmission is triggered by the system.

A trigger event is required for DMA channel transport. QDMA channel transmission can be triggered automatically by setting the trigger word.

Each event queue depth is 16, and a maximum of 16 transmission events are supported at the same time.

The event queue assigned to each DMA and QDMA channel is programmable.

If events are detected at the same time on different channels, the event queue will be arbitrated based on a fixed priority arbitration mechanism. DMA channels have a higher priority than QDMA channels. The lowest numbered channel has the highest priority.

Each event is processed in FIFO order in the event queue.

The channel of DMA and QDMA can be numbered successively together, and TI is handled in this way.

The difference between Global Region and Shadow Region: when using Global Region to configure EDMA, all kernels respond; when using Shadow Region, unwanted events are masked through the DRAE/DRAEH (for DMA) and QRAE/QRAEH (for QDMA) registers, so that even if the events in the system are triggered, the corresponding events in the Shadow Region are not triggered. When you configure EDMA with global region, all core will respond, so that some event that core does not want to use will be triggered. If shadow region is used, the event that you do not want to trigger will be masked through DRE/DREH, so that even if the corresponding event in the system is triggered, the event in shadow region will not be triggered.

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