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This article focuses on "what is the concept of Linux memory management and addressing". Interested friends may wish to take a look. The method introduced in this paper is simple, fast and practical. Let the editor take you to learn "what is the concept of Linux memory management and addressing"?

1. Conceptual memory management mode

Segment type: memory is divided into multiple segments, each segment is continuous memory, different segments correspond to different uses. The size of each segment is not uniform, which will lead to memory fragmentation and inefficient memory swapping.

Page style: memory is divided into multiple memory pages for management, such as in Linux systems, the size of each page is 4KB. Because after paging, there will be no small memory fragments. However, there is still a problem of memory fragmentation.

Segment page style: the combination of paragraph style and page style.

Address type division

Logical address: the address used by a program, which is usually not mapped by segmented memory management, is called a logical address.

Linear address: an address mapped by segmented memory management, called a linear address, also known as a virtual address

Virtual address: an address mapped by segmented memory management, called a linear address, also known as a virtual address

Physical address: physical memory address

Description:

In the Inetel processor, the logical address is the address before "segment memory management" translation, and the linear address is the address before "page memory management" translation.

The address mapped by segmented memory management is no longer a "physical address". Intel calls it a "linear address" (also known as a virtual address). Therefore, segment memory management first maps logical addresses to linear addresses, and then page memory management maps linear addresses to physical addresses.

Linux memory is mainly page-based memory management, but also involves segment mechanism. The current approach taken by the Linux kernel is to make the process of segment mapping virtually ineffective.

Intel's earliest processor 80286 was pure segment management, with both 80386 segments and pages.

two。 Page management x86 architecture 32-bit cpu

Second-level page table location, a memory page 4KB size, first-level page table 1024 items, second-level page table 1024 items, a page table entry 4 bytes. The first-level page catalog table entries are all allocated, and the second-level page table is created when needed. (locality principle).

Virtual address 32-bit

10: 10: 12, index the first-level page table number and the second-level page table item respectively, and record the offset address of the physical base address. After using the PAE mechanism, the maximum memory supported by the 32bit system is 64GB (address is 32 bits 4 bits 36 bits).

Linear address addressing physical address step

First, the address of the level 2 page table is recorded in the level 1 page table number according to the 10-bit addressing.

After finding the address of the level 2 page table, then look for the location of the table item in the level 2 page table according to the other 10 bits of the virtual address

After finding the table entry of the level 2 page table, the starting address of the virtual address mapping physical address is recorded in the table entry, and the size of the table entry is 4 bytes 32bit

The final physical address is calculated from the starting address of the found physical address combined with the last 12 bits of the virtual address as the offset.

X86 architecture 64-bit cpu

There are more page tables

Global page catalog entry PGD (Page Global Directory upper page directory entry PUD (Page Upper Directory) middle page directory entry PMD (Page Middle Directory) page table entry PTE (Page Table Entry)

Linear address addressing physical address step

The linear address is 48bit, the maximum physical address is 52bit, and the actual physical memory address bus width is 40bit, that is, it supports 1TB physical memory x86. 64 has a four-level page table, the principle is the same as x86 system, and layer by layer of addressing CR3 registers store the starting physical address of the highest-level table, so the first thing to address is to get the value in the CR3 register. The size of each PTE entry is 8 bytes, that is, 64bit.

TLB

In the CPU chip, a Cache is added to store the page table items most frequently accessed by the program, and this Cache is TL (Translation Lookaside Buffer). Commonly referred to as page table cache, forwarding bypass cache, fast table, and so on. Then when CPU's memory management unit MMU addresses, it will check the TLB first, and if it cannot find it, it will continue to check the regular page table.

Proper noun

PDT: page catalog table, multi-level page table, one-level page table, 32bit system has 1024 page directories

PTT: page item table, multi-level page table, two-level page table. The 32bit system has 1024 page items under each page directory, each with 4 bytes.

PDE: the base address of the page table, which is an item in PDT

PTE: is the base address of the page and is an item in PTT

GDT: global descriptor table, used to convert logical addresses to linear addresses

LDT: local descriptor table, used to convert logical addresses to linear addresses

3. Address division

32 system

Kernel 1G: 0xC0 00 00 01-0xFF FF FF FF

Subscriber 3G: 0x00 00 00 00-0xC0 00 00 00

0xC0 00 00 00 = 3G

64-bit system:

Kernel 128T: 0xFF FF 80 00 00 00-0xFF FF FF FF FF FF FF FF (high order)

0xFF FF 7F FF FF FF FF FF-0xFF FF FF FF FF FF FF FF (self-calculation)

User 128T: 0x00 00 00 00-0x00 00 7F FF FF FF FF FF (low)

0x00 00 80 00 00 00-0x00 00 80 00 00 00 (self-calculation)

0x00 00 7F FF FF FF FF FF = = 127T

Question: 64-bit system 128T is the dividing line is 127T?

Access permission

When the process is in user mode, it can only access user space memory.

Only when you enter the kernel state can you access the memory in the kernel space.

PAE mechanism

CPU bit width refers to the number of binary bits that CPU can handle in a clock cycle. In common scenarios, the address bus of 32-bit CPU can be 32 bits, but with the introduction of PAE mechanism, the address bus width of 16-bit CPU can be 20 bits (physical memory 1m), the address bus of 32-bit CPU can be 36 bits (physical memory 64GB), and the address bus width of 64-bit CPU can be 40 bits (physical memory 1TB). So we can't simply say that 32-bit systems only support memory sticks with the largest 4GB.

4. Debug

Program register

Cs: is a code snippet register

Ds: is a segment register

Ss: is the stack segment register

Es: is the extended segment register

Fs: it is only available after 32 bits of the flag segment register

Gs: it is only available after 32 bits of the global segment register

For example, a log of kernel downtime:

RIP: 0010: [] [] xxxxxxxxxx+0x69/0x70

RSP: 0018:ffff886241737d98 EFLAGS: 00010246

RAX: ffff880034814d40 RBX: ffff881fc6248740 RCX: 0000000000000200

RDX: 0000000000000000 RSI: 0000000000000286 RDI: ffff881fc6381858

RBP: ffff886241737d98 R08: ffff886241734000 R09: 0000000000000000

R10: ffff880034814d40 R11: 0000000000000200 R12: ffff881fc62487a0

R13: 0000000000000000 R14: 00007fff86cb6260 R15: ffff881fc6381858

FS: 00007f78b59b8720 (0000) GS:ffff885ffe3c0000 (0000) knlGS:0000000000000000

CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033

CR2: 00007f690a057180 CR3: 0000006208985000 CR4: 00000000003627e0

DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000

DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400

View program register

Use GDB to randomly debug an executable file of ELF32 on linux 32-bit, and use the info r command to check the registers:

There are two cases of segment register: 0x23 and 0x2b:

Hexadecimal: 0023

Binary: 0000000000100 011-paragraph serial number: 4-table type: GDT-privilege level: Ring3

Hexadecimal: 002B

Binary: 00000000101 011-paragraph serial number: 5-table type: GDT-privilege level: Ring3

Segment serial number: starting from the fourth position, table type: third privilege level: 1st and 2nd digits

Linux did not find a way to view GDT directly with any command or tool, so go to the source code to find the answer:

See, the segments described in these two items are the same as Windows, with the base address 0 and the size 4GB.

Both Windows and Linux chose to empty CPU's segmented memory management mechanism in this way.

However, it needs to be explained that although this is the case in both operating systems, it does not mean that the segment mechanism is completely useless. The task management TSS of CPU still needs to be used. As we all know, the segmentation mechanism is not popular in Linux 64-bit systems, but the operating system will still maintain the addressing mode of segmenting and then paging.

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