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Analysis of write Operation of SRAM memory

2025-01-21 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > Servers >

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At present, according to different application markets, the technological development of SRAM products has shown two major trends: one is to develop to high-speed devices needed for high-performance communication networks. Because of the fast reading and writing speed, SRAM memory is used as a cache in computers. Improving its reading and writing speed is of positive significance to give full play to the advantages of microprocessors and improve processor performance. The other is to reduce power consumption to adapt to the booming portable application market. Yingshang Microelectronics introduces the analysis of "write operation" in SRAM reading and writing.

Analysis of SRAM write operation

The write operation is the opposite of the read operation, which flips the state of the memory cell according to the written data. Figure 1 shows a schematic diagram of the write operation of the six-tube unit. The bit line BIT_ is driven to a low level at the beginning of the write operation. After the word line opens the transmission tube, the N3 and P1 tubes form a partial voltage between the BIT and the high-level VDD. For the success of the write operation, that is, to pull down node A to a sufficiently low level and start the inverter P2/N2 to enlarge the new data, the transmission tube N3 should have better connectivity than the P1 tube. Once the inverter P2/N2 begins to amplify the low voltage on node A, that is, the pull-down tube N2 on node An is turned off, the pull-up tube P2 is turned on, the voltage of node B will rise, the inverter P1/N1 will also be started, node A will be further converted to GND under positive feedback, and the write operation will be accelerated.

Fig. 1 write operation of six-tube unit

In the write operation of the six-tube unit, the external circuit drives two complementary signals to the bit line BIT and BIT_, the word line driver drives the word line ROW to the high level, and the bit line signal is written to the storage node through the two transmission tubes. As shown in figure 1, it is the case of writing "0" to the cell with "1", that is, pulling down the level of point A from VDD to GND.

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