Shulou(Shulou.com)06/01 Report--

What is the FSMC peripherals of STM32, many novices are not very clear about this, in order to help you solve this problem, the following editor will explain in detail for you, people with this need can come to learn, I hope you can gain something.

01. Characteristics of FSMC

Flexible static memory controller (FSMC) flexible static storage controller. FSMC can connect asynchronous or synchronous memory or 16-bit PC memory cards for the following main purposes:

Convert AHB data communication transactions into appropriate external device protocols

Meet the access timing requirements of external devices

All external memories share addresses, data, and control signals, but have their own chip selection signals. FSMC can only access one external device at a time.

FSMC, a flexible static memory controller, can be connected to synchronous or asynchronous memory and 16-bit PC memory cards. STM32's FSMC interface supports memories such as SRAM, NANDFLASH, NORFLASH and PSRAM.

Block diagram of △ FSMC

02, AHB interface

The AHB device interface enables internal CPU and other main bus peripherals to access external memory. AHB transactions can transmit external device protocols. Especially when the external memory is selected as 8-bit or 16-bit, the 32-bit AHB transmission transaction is divided into multiple consecutive 8-bit or 16-bit transmission transactions. The selection will be switched at each visit.

General transaction rules require that the AHB transmit data width must be 8 bits, 16 bits, or 32 bits. However, access to external data must have a fixed data width. This can lead to different transmissions.

Therefore, some simple transaction rules must be followed:

The AHB transaction data width must be the same as the memory data width. There will be no problem in this case.

The width of AHB transaction data is larger than that of memory data. In this case, FSMC divides AHB transactions into multiple consecutive memory accesses, which conforms to the data width of external memory access.

AHB transaction data has a small memory width, in which case asynchronous transfers may or may not be consistent, depending on the type of external device.

Asynchronous access to the device requires byte selection function (SRAM,ROM,PSRAM), ① FSMC allows write transactions to access appropriate data through its byte selection channel NBL [1:0], and ② allows read transactions. All memory bytes are read and useless memory bytes are discarded. The NBL [1:0] remains low during the read transaction.

Asynchronous access to devices (16-bit NOR and NAND Flash) that do not have byte selection functions, which occurs when byte access to 16-bit wide Flash memory is requested.

Obviously, this device cannot be accessed in byte mode (only 16-bit words can be read or written to Flash memory), so ① does not allow writing transactions and ② allows reading transactions. All memory bytes are read and useless memory bytes are discarded. NBL [1:0] keeps the level low during the read transaction.

03. External device address mapping

External device address image of FSMC, STM32's FSMC divides external storage into four blocks of fixed size 256m bytes:

Block 1 is used for 4 NORflash or PSRAM memory devices. Block 1 is divided into four NORflash/PSRAM blocks with independent chip selection signals.

Blocks 2 and 3 are used to connect NANDflash (one block drives one device)

Block 4 is used to connect PC block devices

For each storage area, the type of memory to be used is defined by the user in the configuration register

HADDR [25:0] contains the external memory address. Because the HADDR is a byte address and the memory is addressed by word, the address actually sent to the memory will vary depending on the width of the memory data, as shown in the following table:

05. External memory interface signal

Non-reuse I/OPSRAM/SRAM

Note: the prefix "N" indicates that the relevant signal is valid at low level.

▽ Mode 1 write access

▽ Mode A write access

It is different from Mode 1 in that NOE switching and independent read and write timing

For Mode A

ADDSET is the high-level time of the NWE, that is, the address establishment time

DATAST is the low level time of NWE, that is, data hold time.

09. The code indicates that readWriteTiming.FSMC_AddressSetupTime = 0x02; / / address setup time (ADDSET) is 2 HCLK 2*1/120M=16nsreadWriteTiming.FSMC_AddressHoldTime = 0x02; / / address hold time (ADDHLD), 16nsreadWriteTiming.FSMC_ DataSetupTime = 0x06; / / data setup time, 50nsreadWriteTiming.FSMC_BusTurnAroundDuration = 0x00 readWriteTiming.FSMC_DataLatency / bus recovery time readWriteTiming.FSMC_CLKDivision = 0x00 / clock frequency division factor readWriteTiming.FSMC_DataLatency = 0x00 / / data generation time readWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A; / / Mode A

FSMC_AddressSetupTime: these bits define the establishment time of the address and are suitable for NOR flash operations in SRAM, ROM, and asynchronous bus multiplexing modes.

FSMC_AddressHoldTime: these bits define the hold time of the address and are suitable for NOR flash operations in SRAM, ROM, and asynchronous bus multiplexing modes.

FSMC_DataSetupTime: these bits define the hold time of data and are suitable for NOR flash operations in SRAM, ROM, and asynchronous bus multiplexing modes.

FSMC_BusTurnAroundDuration: these bits are used to define the delay on the bus after a read operation (for NOR flash operations in bus multiplexing mode only). After a read operation, the controller needs to send an address on the data bus for the next operation. This delay is to prevent bus conflicts. If the extended memory system does not contain bus multiplexing mode memory, or if the slowest memory can restore the data bus to the high resistance state within six HCLK clock cycles, this parameter can be set to its minimum value.

FSMC_CLKDivision: defines the period of the CLK clock output signal, expressed as the number of HCLK cycles.

FSMC_DataLatency: NOR flash memory in synchronous grouping mode needs to define the number of memory cycles to wait before reading the first data. This time parameter is not expressed in HCLK, but in flash memory clock (CLK). This parameter does not work when accessing asynchronous NOR flash, SRAM, or ROM. This parameter must be 0 when operating on CRAM

FSMC_AccessMode: access mode

FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;// here we use NE1, which corresponds to BTCR [6], [7]. FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;// unreused data address FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;// FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;// memory data width is 8bit FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;// memory write enable FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;// read and write use the same timing FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = & readWriteTiming;// read and write timing FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = & readWriteTiming;// write timing

FSMC_Bank:nor is divided into four blocks, where this parameter indicates that the block is programmed.

FSMC_DataAddressMux: whether the address\ data is reused

FSMC_MemoryType: storage type

FSMC_MemoryDataWidth: data bus width 8 bits / 16 bits

FSMC_BurstAccessMode: whether to access in group mode

FSMC_WaitSignalPolarity: waiting for signal availability level

FSMC_WrapMode: this bit determines whether the controller supports splitting an unaligned AHB group operation into two linear operations; this bit is valid only in the grouping mode of the memory.

FSMC_WaitSignalActive: when the flash memory is in group transmission mode, the NWAIT signal indicates whether the data coming out of the flash memory is valid or whether it needs to be inserted into the waiting period. The bit determines whether the memory generates a NWAIT signal in a clock cycle before the wait state, or whether a NWAIT signal is generated during the wait state.

FSMC_WriteOperation: this bit indicates whether the FSMC allows / disables write operations to the memory.

FSMC_WaitSignal: when the flash memory is in group transfer mode, this bit allows / disables insertion into the waiting state through the NWAIT signal.

FSMC_ExtendedMode: this bit allows FSMC to use FSMC_BWTR registers, that is, to allow different timing for reading and writing.

FSMC_WriteBurst: for flash memory in group transfer mode, this bit allows / disables insertion into the waiting state through NWAIT signals. The synchronous group transfer protocol for read operations enables the BURSTENbit of the FSMC_BCRx register.

FSMC_ReadWriteTimingStruct: read timing configuration pointer

FSMC_WriteTimingStruct: write timing configuration pointer

Is it helpful for you to read the above content? If you want to know more about the relevant knowledge or read more related articles, please follow the industry information channel, thank you for your support.

Welcome to subscribe "Shulou Technology Information " to get latest news, interesting things and hot topics in the IT industry, and controls the hottest and latest Internet news, technology news and IT industry trends.