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This article will explain in detail what the working principle of FPGA is, and the content of the article is of high quality, so the editor will share it with you for reference. I hope you will have a certain understanding of the relevant knowledge after reading this article.

As mentioned earlier, FPGA is the product of further development on the basis of programmable devices such as PAL, GAL, EPLD, CPLD and so on. It appears as a kind of semi-custom circuit in the field of ASIC, which not only solves the deficiency of custom circuit, but also overcomes the limitation of original programmable device gate circuit.

Because FPGA needs to be written repeatedly, the basic structure of combinational logic can not be completed through fixed and non-gates like ASIC, but can only adopt a structure that is easy to be configured repeatedly. The look-up table can meet this requirement very well. At present, the mainstream FPGA adopts the look-up table structure based on SRAM process, and some military and aerospace FPGA use Flash or fuse and anti-fuse process look-up table structure. The repeated configuration of FPGA is realized by burning and writing files to change the contents of the lookup table.

According to the basic knowledge of digital circuits, it can be known that for an n-input logic operation, whether it is and or non-operation, XOR operation and so on, there can be at most 2n results. Therefore, if the corresponding results are stored in a storage unit in advance, it is equivalent to realizing the function of the non-gate circuit. The same is true of the principle of FPGA. It configures the contents of the lookup table by burning and writing files, thus realizing different logic functions in the same circuit.

The Look-Up-Table, or LUT,LUT for short, is essentially a RAM. Currently, 4-input LUT is often used in FPGA, so each LUT can be regarded as a RAM with 4-bit address lines. When the user describes a logic circuit through the schematic diagram or HDL language, the PLD/FPGA development software will automatically calculate all the possible results of the logic circuit and write the truth table (that is, the result) into RAM in advance, so that each input signal for logical operation is equal to inputting an address to look up the table, find out the corresponding content of the address, and then output it.

The following is an example of a 4-gate circuit to illustrate the principle of LUT to achieve logic functions.

Example 1-1: a truth table of 4 input and gate circuits using LUT is given.

Table 1-14 Truth table of inputs and doors

It can be seen that LUT has the same function as logic circuit. In fact, LUT has faster execution speed and larger scale.

Because the FPGA based on LUT has a high degree of integration, its device density varies from tens of thousands of gates to tens of millions of gates, and can complete extremely complex sequential and logic combinational logic circuit functions, so it is suitable for high-speed, high-density high-end digital logic circuit design field. Its main components are programmable input / output unit, basic programmable logic unit, embedded SRAM, rich wiring resources, bottom embedded functional unit, embedded special unit and so on. The main designers and manufacturers are Xilinx, Altera, Lattice, Actel, Atmel and QuickLogic, among which the largest are Xilinx, Altera and Lattice.

As mentioned earlier, the working status of FPGA is set by the RAM stored in the chip, so it is necessary to program the on-chip RAM when working. Users can adopt different programming methods according to different configuration modes. FPGA has the following configuration modes:

Parallel mode: parallel PROM, Flash configuration FPGA

Master-slave mode: one piece of PROM with multiple pieces of FPGA

Serial mode: serial PROM configuration FPGA

Peripheral mode: FPGA is used as the peripheral of the microprocessor, which is programmed by the microprocessor.

At present, the FPGA produced by Xilinx and Altera, the two major companies with the highest market share of FPGA, are based on SRAM process, which requires an off-chip memory to save the program. When powering up, the FPGA reads the data from the external memory into the on-chip RAM, and after completing the configuration, it enters the working state; after the power is off, the FPGA is restored to white film, and the internal logic disappears. In this way, FPGA can not only be used repeatedly, but also need no special FPGA programmer, but only general EPROM and PROM programmer. Actel, QuickLogic and other companies also provide anti-fuse technology FPGA, which can only be downloaded once, with the advantages of anti-radiation, high and low temperature resistance, low power consumption and high speed, etc., and is widely used in military and aerospace fields, but this kind of FPGA can not be erased and written repeatedly, so it is troublesome in the initial stage of development and expensive. Lattice is the inventor of ISP technology, which has certain characteristics in small-scale PLD applications. The early Xilinx products generally did not involve the military and aerospace markets, but at present, a number of products such as Q Pro-R have entered this field.

1.2.2 FPGA chip structure

At present, the mainstream FPGA is still based on look-up table technology, which has far exceeded the basic performance of previous versions, and integrates hard-core (ASIC) modules with common functions such as RAM, clock management and DSP. As shown in figure 1-1 (Note: figure 1-1 is only a schematic diagram, in fact, each series of FPGA has its own corresponding internal structure), the FPGA chip is mainly completed by six parts, namely: programmable input and output unit, basic programmable logic unit, complete clock management, embedded block RAM, rich wiring resources, embedded underlying functional unit and embedded special hardware module.

Figure 1-1 Internal structure of FPGA chip

The functions of each module are as follows:

1. Programmable input / output unit (IOB)

The programmable input / output unit is referred to as the I / O unit, which is the interface part of the chip and the external circuit, which completes the requirements of driving and matching the input / output signals under different electrical characteristics. Its schematic structure is shown in figure 1-2. ICandle O in FPGA is classified according to groups, and each group can independently support different Imax O standards. Through the flexible configuration of the software, it can adapt to different electrical standards and the physical characteristics of Icano, adjust the driving current, and change the up and down resistors. At present, the frequency of I / O ports is getting higher and higher, and some high-end FPGA can support data rates as high as 2Gbps through DDR register technology.

Figure 1-2 A typical diagram of the internal structure of IOB

The external input signal can be input into the FPGA through the storage unit of the IOB module, or directly into the FPGA. When the external input signal is input into the FPGA through the memory unit of the IOB module, its hold time (Hold Time) requirement can be reduced, usually the default is 0.

In order to facilitate management and adapt to a variety of electrical standards, the IOB of FPGA is divided into several groups (bank). The interface standard of each bank is determined by its interface voltage VCCO. A bank can only have one kind of VCCO, but the VCCO of different bank can be different. Only ports with the same electrical standard can be connected together, and the same VCCO voltage is the basic condition of the interface standard.

2. Configurable logical block (CLB)

CLB is the basic logical unit in FPGA. The actual number and characteristics of CLB vary from device to device, but each CLB contains a configurable switch matrix consisting of 4 or 6 inputs, some selection circuits (multiplexers, etc.), and triggers. The switch matrix is highly flexible and can be configured to handle combinational logic, shift registers, or RAM. In Xilinx's FPGA devices, CLB consists of multiple (usually 4 or 2) identical Slice and additional logic, as shown in figure 1-3. Each CLB module can not only be used to implement combinational logic and temporal logic, but also can be configured as distributed RAM and distributed ROM.

Figure 1-3 schematic diagram of a typical CLB structure

Slice is the basic logic unit defined by Xilinx. Its internal structure is shown in figure 1-4. A Slice consists of two 4-input functions, carry logic, arithmetic logic, storage logic and function multiplexer. Arithmetic logic includes an exclusive OR gate (XORG) and a dedicated and gate (MULTAND). An exclusive OR gate enables a Slice to fully add 2bit, and the special and gate is used to improve the efficiency of the multiplier; the carry logic consists of a special carry signal and function multiplexer (MUXC) for fast arithmetic addition and subtraction operations The 4-input function generator is used to realize 4-input LUT, distributed RAM or 16-bit shift register (the two input functions in the Slice of Virtex-5 series chips are 6 inputs, which can realize 6-input LUT or 64-bit shift register); the carry logic includes two fast carry chains to improve the processing speed of the CLB module.

Figure 1-4 schematic diagram of typical 4-input Slice structure

3. Digital clock Management Module (DCM)

Most FPGA in the industry provide digital clock management (all FPGA of Xilinx have this feature). Xilinx introduces the state-of-the-art FPGA to provide digital clock management and phase loop locking. Phase loop locking can provide accurate clock synthesis, reduce jitter and achieve filtering functions.

4. Embedded block RAM (BRAM)

Most FPGA have embedded block RAM, which greatly expands the application scope and flexibility of FPGA. Block RAM can be configured as a common storage structure such as single-port RAM, dual-port RAM, content address memory (CAM) and FIFO. RAM and FIFO are popular concepts, so we won't elaborate on them here. The CAM memory has a comparison logic in each of its internal storage cells, and the data written into the CAM is compared with each internal data and returns the address of all the data that is the same as the port data, so it is widely used in routed address switches. In addition to block RAM, LUT in FPGA can be flexibly configured into structures such as RAM, ROM, and FIFO. In practical application, the number of RAM in the chip is also an important factor in selecting the chip.

The capacity of a single chip RAM is 18k bits, that is, the bit width is 18 bits and the depth is 1024. The bit width and depth can be changed as needed, but two principles must be met: first, the modified capacity (bit width depth) should not be greater than 18k bits; secondly, the maximum bit width should not exceed 36 bits. Of course, multiple blocks of RAM can be cascaded together to form a larger RAM, which is only limited by the number of RAM blocks on the chip, rather than by the above two principles.

5. Rich cabling resources

The wiring resource connects all the units within the FPGA, and the length and process of the connection determine the driving ability and transmission speed of the signal on the connection. There are abundant wiring resources in the FPGA chip, which are divided into four different categories according to the process, length, width and distribution location. The first type is global cabling resources, which are used for global clock and global reset / set cabling within the chip; the second kind is long-line resources, which are used to complete the routing of high-speed signals and the second global clock signal between chip Bank; the third kind is short-line resources, which are used to complete logical interconnection and routing between basic logic units; and the fourth kind is distributed cabling resources, which are used for proprietary clock, reset and other control signal lines.

In practice, the designer does not need to select routing resources directly, and the layout router can automatically select routing resources to connect each module unit according to the topology and constraints of the input logical Netlist. In essence, the use of wiring resources is closely and directly related to the results of the design.

6. Underlying embedded functional unit

Embedded functional modules mainly refer to soft processing cores (Soft Core) such as DLL (Delay Locked Loop), PLL (Phase Locked Loop), DSP and CPU. Now more and more rich embedded functional units, making a single FPGA has become a system-level design tool, so that it has the ability of software and hardware co-design, and gradually transition to the SOC platform.

DLL and PLL have similar functions, such as frequency doubling and frequency division with high precision and low jitter, as well as duty cycle adjustment and phase shift. Xilinx's chip integrates DLL,Altera 's chip and PLL,Lattice 's new chip integrates PLL and DLL at the same time. PLL and DLL can be easily managed and configured through tools generated by the IP core. The structure of DLL is shown in figure 1-5.

7. Embedded dedicated hard core

Embedded special hard core is relative to the soft core embedded in the bottom layer, which refers to the hard core (Hard Core) with powerful FPGA processing capacity, which is equivalent to the ASIC circuit. In order to improve the performance of FPGA, chip manufacturers have integrated some special hard cores in the chip. For example, in order to improve the multiplication speed of FPGA, special multipliers are integrated in the mainstream FPGA; in order to adapt to the communication bus and interface standards, many high-end FPGA are integrated with serial-parallel transceivers (SERDES), which can achieve the sending and receiving speed of dozens of Gbps.

Xilinx's high-end products not only integrate Power PC series CPU, but also embed DSP Core modules. The corresponding system-level design tools are EDK and Platform Studio, and the concept of system-on-chip (System on Chip) is proposed. Through PowerPC, Miroblaze, Picoblaze and other platforms, we can develop standard DSP processors and related applications to achieve the purpose of SOC development.

1.2.3 Concepts of soft core, hard core and solid core

IP (Intelligent Property) core is the general name of integrated circuit core with intellectual property core, which has been verified repeatedly and has specific functions. It has nothing to do with the chip manufacturing process and can be transplanted to different semiconductor processes. To the SOC stage, IP core design has become an important task of ASIC circuit design company and FPGA provider, and it is also the embodiment of its strength. For FPGA development software, the richer the IP core it provides, the more convenient the user's design will be, and the higher its market share will be. At present, IP core has become the basic unit of system design, and has been exchanged, transferred and sold as independent design results.

IP cores are usually divided into three types: soft core, hard core and fixed core. In terms of the cost of completing the IP core, the hard core is the highest; in terms of flexibility, the soft core has the highest reusability.

1. Soft core

In the field of EDA design, soft core refers to the register transfer level (RTL) model before synthesis; in FPGA design, it refers to the hardware language description of the circuit, including logic description, Netlist and help documents. The soft core only goes through functional simulation and needs synthesis and layout before it can be used. Its advantages are high flexibility, strong portability, allowing users to configure themselves; the disadvantage is that the prediction of the module is low, there is a possibility of errors in the follow-up design, there is a certain design risk. Soft core is the most widely used form of IP core.

2. Fixed core

In the field of EDA design, the fixed core refers to the Netlist with plane planning information; specifically, in FPGA design, it can be regarded as the soft core with layout planning, which is usually provided in the mixed form of RTL code and the corresponding specific process Netlist. The RTL description is combined with the specific standard cell library for comprehensive optimization design to form a gate-level Netlist, and then it can be used through the layout and routing tool. Compared with the soft core, the design flexibility of the fixed core is slightly less, but the reliability is greatly improved. At present, fixed nuclei are also one of the mainstream forms of IP nuclei.

3. Hard core

Hardcore in the field of EDA design refers to the verified design layout; specifically in FPGA design refers to the design with fixed layout and process, front-end and back-end verification, designers can not modify it. Can not be modified for two reasons: first, the system design of each module timing requirements are very strict, do not allow to disrupt the existing physical layout; second, the protection of intellectual property rights requirements, designers are not allowed to have any changes to it. The no modification feature of IP hard core makes it difficult to reuse, so it can only be used in some specific applications and the scope of use is narrow.

About what the working principle of FPGA is shared here, I hope the above content can be of some help to you, can learn more knowledge. If you think the article is good, you can share it for more people to see.

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