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This article is to share with you about the general structure of SERDES, the editor thinks it is very practical, so I share it with you to learn. I hope you can get something after reading this article.

The basic structure of SERDES

To put it simply, the basic block diagram of SERDES is as follows:

SERDES block diagram

It is probably composed of transmit line, receive line, serialization module, clock management module, coding and decoding module, transmit and receive buffer module (FIFO) and Alignment module. In fact, there is a user logic module customized by the user according to the specific content of the interface protocol, which is used to generate send data and parse and receive data, which is the only place where users can handle flexibly, and where logic engineers can carry out circuit design (Verilog design).

Among them, the transmitting line, that is, the tx Line interface in the figure and the receiving line (Rx Line Interface) are serial lines that interact with external chips, which can be composed of one or more pairs of differential signal lines respectively. Generally speaking, 1 pair is called X1 pattern, 2 pairs are X2, and so on, n pair is Xn. The more such differential signal lines, the greater the bandwidth of data transmission. If the transmission bandwidth of a pair of differential signal lines is 3.125Gbps, then the n pair is n*3.125Gbps.

The serialization module (Serializer) is the parallel-serial conversion (PISO) module. The user logic generates the data to be sent, encodes the 8B/10B or other types of code, scrambles, enters the buffer and waits for operation, and finally through the parallel-serial conversion module, the serial data is converted into serial data and sent through the transmission line. Similarly, the de-serialization module (Deserializer) is the inverse process of the serialization module, that is, the serial data received by the serial differential line is converted into parallel data through the serial-parallel conversion (SIPO) module, and then the parallel data after decoding, descrambling, and other operations are given to the user interface, and the user parses the parallel data.

Why is there a Transmit and Receiver buffers/FIFO in the image above?

One of the most important functions of this module is to convert across clock domains! Since there is more than one clock involved in SERDES, take the transmitting part of a channel of our Xilinx's Transceiver, as shown in the following figure:

TX clock domain

You can ignore the other parts for the time being. I will specifically introduce the following articles about the Transceiver of Xilinx home. We only look at its clock domain partition to see why there is such a thing as cross-clock domain processing. The function of the Phase Adjust FIFO in the above figure is the specific design of the Transmit and Receiver Buffers/FIFO in the general SERDES. The problem to be solved is that in order to transfer data between two clock domains, rate matching must be carried out, and all the phase differences between the two clock domains must be solved. To put it simply, it is cross-clock domain processing. In cross-clock domain processing, FIFO is the most commonly used processing method for data transmission between two different clock domains, which is the focus of written interviews at any time. I prepared the relevant content when I was a student, see:

Minimization of basic knowledge of FPGA (7) detailed explanation of metastable state and cross-clock domain transmission

As for the clock management module, it is obvious that it manages all kinds of clock problems, including clock division, frequency doubling and clock recovery.

The general architecture of SERDES is simply dictated on, which seems to be disorganized. A general SERDES block diagram is given below, and each module is simply defined.

General block diagram of SERDES

As shown in the following figure, is the general block diagram of SERDES, which is a refinement of the SERDES block diagram in the previous section. The definition of each module is given below.

SERDES general block diagram serializer (Serializer): obtains n-bit parallel data at a rate of y, and then converts it into a serial data stream at a rate of n times y; Deserializer: acquires a serial data stream at the rate of y of n and converts it into parallel data with a width of y at a rate of y; Rx (Receive) Align: Rx (receive) alignment: aligns the input data to the appropriate word boundary. Several different mechanisms can be used, from automatically detecting and aligning a special sequence of reserved bits (commonly referred to as Comma) to user-controlled bit slips; clock Manager (Clock Manager): managing various clock requirements, including clock frequency doubling, clock frequency division and clock recovery; sending FIFO (Transmit FIFO): allows incoming user data to be stored before sending Receive FIFO (Receive FIFO): allows storage of received data (cache data) before deletion; critical in systems that require clock correction; receiver line interface: analog receiver circuit includes differential receiver and can include active or passive equalization; transmission line interface: analog transmission circuit usually allows for different drive intensities. It also allows pre-accentuated emission; Line Encoder: encodes the data into a more friendly data format. This usually involves eliminating the invariant bits of a long sequence. The data may also be adjusted to achieve a balance and zero balance. (this is an optional block that is sometimes not included in the SERDES. ); line decoder: decoding from line-encoded data to pure data. (this is an optional block, sometimes done outside of SERDES. Clock correction and channel binding: allows you to correct the difference between the sending clock and the receiving clock. Skew correction between multiple channels is also allowed. Channel binding is optional and is not always included in the SERDES. )

Other possible features can be included, such as a cyclic redundancy check (CRC) generator, a CRC checker, multiple encodings and decoders of 4b / 5b, 8b / 10b, 64b / 66b, configurable scramblers, various alignment and daisy chain options, and front and back ends of configurable clocks.

SERDES or Transceiver display on the market

The architectures of two gigabit transceivers are listed below, but this article will not explain them in detail for the time being, which will be introduced later in this series.

Transceiver Architecture presentation of Xilinx

To simplify browsing, we only give the structure of the Transceiver of one channel (7 series FPGA as an example):

Introduction to the structure of Transceiver by SERDES of Altera

Virtex ™- II Pro X RocketIO ™SERDES structure block diagram:

SERDES block diagram

Virtex-II Pro RocketIO SERDES structure block diagram:

The SERDES block diagram above is what the general structure of SERDES is. The editor believes that there are some knowledge points that we may see or use in our daily work. I hope you can learn more from this article. For more details, please follow the industry information channel.

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