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This article mainly introduces the relevant knowledge of what matters needing attention in the use of the Cortex-M kernel of the FreeRTOS real-time operating system, the content is detailed and easy to understand, the operation is simple and fast, and has a certain reference value. I believe you will gain something after reading this article on the precautions for the use of the Cortex-M kernel of the FreeRTOS real-time operating system. Let's take a look.

1. 1.1Cortex-M hardware description of valid priority

First of all, you need to know the total number of valid priorities, depending on how the microcontroller manufacturer uses the Cortex kernel. Therefore, not all Cortex-M kernel microprocessors have the same interrupt priority level.

The Cortex-M architecture itself allows up to 256 programmable priorities (priority configuration registers up to 8 bits, so priorities range from 0x00~0xFF), but most microcontroller manufacturers use only some of these priorities. For example, the TI Stellaris Cortex-M3 and Cortex- M4 microcontrollers use three bits of the priority configuration register to provide an 8-level priority. For example, the NXP LPC17xx Cortex- M3 microcontroller uses five bits of the priority configuration register to provide a 32-level priority.

1.2 apply to RTOS

The RTOS interrupt nesting scheme divides the effective interrupt priority into two groups: one group can be masked by the RTOS critical section, and the other group is not affected by RTOS and is always enabled. The macro configMax _ SYSCALL_INTERRUPT_PRIORITY is configured in FreeRTOSConfig.h to define the boundary between two sets of interrupt priorities. Interrupts whose logical priority is higher than this value are not affected by RTOS. The optimal value depends on the number of bits of the priority configuration register used by the microcontroller.

two。 Priority values and logical priority settings contrary to numeric values 2.1Cortex-M hardware details

It is necessary to explain the priority value and logical priority first: in the Cortex-M kernel, if there is an 8-level priority, we say that the priority value is 0-7, but the highest numerical priority 7 represents the lowest logical priority. Many engineers who use the traditional interrupt priority architecture will find this counterintuitive and counterintuitive. The priorities mentioned below should be carefully distinguished between priority values and logical priorities.

The next thing to be clear is that in the Cortex-M kernel, the lower the priority value of an interrupt, the higher the logical priority. For example, an interrupt with an interrupt priority of 2 can preempt an interrupt with an interrupt priority of 5, but not vice versa. In other words, interrupt priority 2 is higher than interrupt priority 5.

This is the most error-prone aspect of the Cortex-M kernel, because most non-Cortex-M kernel microcontrollers have the opposite interrupt priority statement.

2.2 apply to RTOS

FreeRTOS functions that end with "FromISR" are protected by interrupt calls (execution of these functions enters the critical section), but even these functions cannot be called by interrupt service functions that have a logical priority over configMAX_SYSCALL_INTERRUPT_PRIORITY. (the macro configMax _ SYSCALL_INTERRUPT_PRIORITY is defined in the header file FreeRTOSConfig.h). Therefore, the interrupt priority value of any interrupt service routine that uses the RTOSAPI function is greater than or equal to the value of the configMAX_SYSCALL_INTERRUPT_PRIORITY macro. This ensures that the logical priority of the interrupt is equal to or lower than configMAX_SYSCALL_INTERRUPT_PRIORITY.

Cortex interrupts have a priority of 0 by default. In most cases, 0 represents the highest priority. Therefore, the RTOSAPI function must not be called in an interrupt service routine with a priority of 0.

3.Cortex-M Internal priority Overview 3.1Cortex-M hardware detail

The interrupt priority register of the Cortex-M kernel is aligned with the highest bit (MSB). For example, if three bits are used to express priority, the three bits are located in the bit5, bit6, and bit 7 bits of the interrupt priority register. The remaining bit0~bit4 can be set to any value, but for compatibility, it is best to set them to 1. 0.

The Cortex-M priority register has up to 8 bits, and if a microcontroller uses only 3 bits, then these 3 bits are aligned with the highest bit, as shown in the following figure:

A microcontroller uses only 3 bits in the priority register. The following figure shows how the priority value 5 (binary 101B) is stored in the priority register. If there is an unused position 1 in the priority register, the following figure also shows why the value 5 (binary 0000 0101B) can be regarded as 191 (binary 1011 1111).

A microcontroller uses only 4 bits in the priority register. The following figure shows how the priority value 5 (binary 101B) is stored in the priority register. If there is an unused position 1 in the priority register, the following figure also shows why the value 5 (binary 0000 0101B) can be regarded as 95 (binary 0101 1111).

3.2 apply to RTOS

As described above, the interrupt logical priority of those calling the RTOS API function in the interrupt service routine must be lower than or equal to configMAX_SYSCALL_INTERRUPT_PRIORITY (low logical priority means high priority value).

CMSIS and different microcontroller vendors provide library functions that can set an interrupt priority. The parameters of some library functions are aligned with the lowest bit, while the parameters of other library functions may be aligned with the highest bit, so you should consult the application manual of the library function to set it correctly.

You can set the values of macros configMax _ SYSCALL_INTERRUPT_PRIORITY and configKERNEL_INTERRUPT_PRIORITY in FreeRTOSConfig.h. These two macros need to be set up according to the Cortex-M kernel itself and aligned with the most significant bits. For example, if a microcontroller uses 3 bits in the interrupt priority register and sets the value of configKERNEL_INTERRUPT_PRIORITY to 5, the code is:

# define configKERNEL_INTERRUPT_PRIORITY (5

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