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This article mainly introduces the example analysis of Linux kernel memory management architecture, which is very detailed and has certain reference value. Friends who are interested must finish it!

Memory management hardware architecture

Because memory management is the core function of the kernel, for memory management performance optimization, in addition to software optimization, hardware architecture has also done a lot of optimization design. The following figure shows a design scheme of memory hierarchy on current mainstream processors.

As can be seen from the figure, three optimization paths are designed for read-write memory.

1) first of all, L1 cache supports virtual address addressing, which ensures that the virtual address (VA) from CPU can be used to directly look up L1 cache without being translated into physical address (PA), thus improving the efficiency of cache lookup. Of course, using VA to find cache, there are security and other defects, which requires CPU to do some special design to make up for, you can read "computer architecture: quantitative research methods" to understand the relevant details.

2) if L1 cache misses, address translation is required to convert VA to PA. The memory mapping management of linux is realized through the page table, but the page table is placed in memory, so it is very inefficient if memory is accessed once in each address translation process. Here CPU accelerates address translation through the TLB hardware unit.

3) after obtaining the PA, look for the cached data in the L2 cache. L2 cache is generally an order of magnitude larger than L1 cache, and its lookup hit rate is higher. If you hit to get the data, you can avoid accessing the memory and improve the access efficiency.

It can be seen that in order to optimize memory access efficiency, modern processors introduce multi-level cache, TLB and other hardware modules (such as the following figure is an 8-core MIPS processor hardware block diagram). There are a large number of design details within each hardware module, which is no longer in-depth here. If you are interested, you can read books such as "computer Architecture: quantitative Research methods" for further understanding.

Memory mapping space partition

According to the needs of different memory usage and usage scenarios, the kernel divides the memory-mapped address space into several parts, each with its own start-stop address, allocation interface and usage scenario. The following figure shows a common 32-bit address space partition structure.

DMA memory dynamically allocates address space: some DMA devices cannot access all memory space because of their own addressing capabilities. For example, early ISA devices can only execute DMA in a 24-bit address space, that is, they can only access the former 16MB memory. Therefore, it is necessary to divide the DMA memory dynamic allocation space, namely DMA zone. Its allocation is applied through the kmalloc interface with the GFP_ATOMIC control character.

Direct memory dynamic allocation of address space: due to access efficiency and other reasons, the kernel uses a simple linear mapping to memory, but because of the addressing ability of 32-bit CPU (4G size) and the initial setting of kernel address space (3G start), it will lead to insufficient address space resources in the kernel. When memory is larger than 1GB, all memory cannot be mapped directly. The part of the address space that cannot be mapped directly, namely highmem zone. The area between DMA zone and highmem zone, normal zone, is mainly used for dynamic memory allocation of the kernel. Its allocation is applied for through the kmalloc interface.

High-end memory dynamically allocates address space: the memory allocated by high-end memory is memory with contiguous virtual addresses but discontiguous physical addresses, which is generally used for modules and drivers dynamically loaded by the kernel, because the kernel may run for a long time and the memory page fragmentation is serious. If you want to apply for a memory page with a large contiguous address, it is difficult to easily lead to allocation failure. According to the needs of the application, high-end memory allocation provides multiple interfaces:

Vmalloc: specify allocation size, page location, and virtual address implicit allocation

Vmap: specifies an array of page locations, and virtual addresses are implicitly assigned

Ioremap: specifies the physical address and size, and the virtual address is implicitly assigned.

Persistent mapping address space: kernel context switching is accompanied by TLB refresh, which results in performance degradation. However, some modules that use high-end memory also have high performance requirements. When the persistent mapping space is switched in the kernel context, its TLB is not refreshed, so the high-end address space they map is more efficient. Its allocation is applied for through the kmap interface. The difference between kmap and vmap is that vmap can map a set of page, that is, page is not contiguous, but the virtual address is contiguous, while kmap can only map one page to the virtual address space. Kmap is mainly used in fs, net and other modules that have high performance requirements for high-end memory access.

Fixed mapping address space: the problem with persistent mapping is that it may sleep and is not available in scenarios that cannot be blocked, such as interrupt contexts, spin lock critical areas, and so on. In order to solve this problem, the kernel is divided into fixed mappings, and its interfaces do not sleep. The fixed mapping space is mapped through the kmap_atomic interface. The usage scenario of kmap_atomic is similar to that of kmap. It is mainly used in modules such as mm, fs, net that require high performance for high-end memory access and cannot sleep.

Different CPU architectures differ in address space division, but in order to ensure that CPU architecture differences are invisible to external modules, the semantics of the memory address space allocation interface are consistent.

Because 64-bit CPU generally does not need high-end memory (of course, it can also support it), it is quite different from 32-bit CPU in address space partition. The following figure shows a kernel address space partition diagram of MIPS64 CPU.

Memory management software architecture

The core work of kernel memory management is memory allocation and recycling management, which is divided into two systems: page management and object management. The page management system is a two-level hierarchical structure, and the object management system is a three-level hierarchical structure. The negative impact of allocation costs and operations on CPU cache and TLB increases gradually from top to bottom.

Page management hierarchy: a two-tier structure composed of cold and hot cache and partner system. Responsible for caching, allocating and recycling memory pages.

Object management hierarchy: a three-level structure composed of per-cpu cache, slab cache and partner system. Responsible for caching, allocating and recycling objects. The object here refers to a block of memory that is less than one page size.

In addition to memory allocation, memory release also operates according to this hierarchy. If the object is released, it is first released to the per-cpu cache, then to the slab cache, and finally to the partner system.

There are three main modules in the block diagram, namely, the partner system, the slab allocator, and the per-cpu (hot and cold) cache. Their comparative analysis is as follows.

These are all the contents of the article "sample Analysis of Linux Kernel memory Management Architecture". Thank you for reading! Hope to share the content to help you, more related knowledge, welcome to follow the industry information channel!

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