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This article shows you what are the nine steps of the CPU interrupt response process, which are concise and easy to understand, which will definitely brighten your eyes. I hope you can get something through the detailed introduction of this article.

CPU responds to an interrupt, which means that CPU is going to execute the corresponding interrupt service program. The response process is that CPU pushes the instruction address of the current execution program into the stack and jumps to the entry address of the interrupt service program. The entry address of the interrupt service program is the interrupt vector, which is stored in two 16-bit registers. The entry address is 22 bits, the lower 16 bits of the address are stored in the lower 16 bits of the vector, the high 16 bits of the address are stored in its high 6 bits, and the higher 10 bits are reserved.

Step 1: any PIE interrupt group's peripherals or external interrupts produce interrupts. If the interrupt in the peripheral module is enabled, the interrupt request will be sent to the PIE module.

Step 2: the PIE module will identify the y interrupt (INTx.y) application in other PIE interrupt group x, and then the corresponding PIE interrupt flag bit is locked: PIEIFRx.y=1.

Step 3: if you want to send the interrupt of PIE to CPU, you need to meet the following two conditions:

1. The corresponding enable bit must be set (PIEIERx.y=1).

two。 The corresponding PIEACKx bits must be cleared.

Step 4: if the two conditions in step 3 are met, the interrupt request is sent to CPU and the corresponding response register bit is set to 1 (PIEACKx=1). The PIEACKx bit will remain the same unless it is cleared in order for other interrupts in this group to request to CPU.

Step 5: the CPU interrupt flag bit is set (CPUIFRx=1), indicating that a CPU-level pending interrupt is generated.

Step 6: if the CPU interrupt is enabled (CPUIERx=1, or DBGIERx=1) and the global interrupt is enabled (INTM=0), CPU will handle the interrupt INTx.

Step 7: CPU recognizes the interrupt and automatically saves the relevant interrupt information, clears the enable register (IER) bit, sets INTM, and clears EALLOW. CPU completes these tasks and prepares to execute the interrupt service program.

Step 8: CPU gets the interrupt vector of the response from PIE.

Step 9: for multiplexing interrupts, the PIE module uses the values in the PIEIERx and PIEIFRx registers to determine the vector address that responds to the interrupt. There are two situations:

1. If a higher priority interrupt is generated in step 4, and the PIEIERx register is enabled, and the corresponding bit of the PIEIFRx is suspended, the higher priority interrupt is first responded to.

two。 If no pending interrupts are enabled in this group, PIE will respond to the highest priority interrupt in the group and transfer the address to use INTx.1. This operation is equivalent to the processor's TRAP or INT instructions.

When CPU enters the interrupt service program, the PIEIFRx.y bit is cleared. It is important to note that the PIEIERx register is used to determine the interrupt vector, which must be noted when clearing the PIEIERx register.

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