Shulou(Shulou.com)06/01 Report--

Today, I will talk to you about what the four transmission methods of 8237dma are, which may not be well understood by many people. In order to make you understand better, the editor has summarized the following contents for you. I hope you can get something from this article.

8237A has four working modes: single-byte transfer, block transfer, request transfer and multi-chip cascading. (1) single-byte transfer (single mode) single-byte transfer means that only one byte is transmitted each time the DMA is transferred. After a byte is transferred, the current byte counter minus 1, the address register plus 1 or minus 1 becomes invalid, release bus control and return control to CPU. If the transmission causes the byte counter to be reduced to 0 or when a signal is generated by the peripheral, the DMA transmission is terminated. The characteristic of single-byte transfer is that it is inefficient to transfer one byte at a time, but it ensures that between two DMA transfers, CPU has the opportunity to gain bus control and execute a CPU bus cycle. (2) data Block transfer (block mode) in this data transfer mode, once 8237A acquires bus control, it will continuously transmit data blocks until the current byte counter is reduced to zero or when a signal is generated by a peripheral, DMA transmission is terminated and bus control is released. The characteristic of data block transfer mode is that it is efficient to transmit one data block at a time, but during the whole DMA transmission, CPU can not control the bus for a long time (unable to respond to other DMA requests, unable to handle other interrupts, etc.). (3) request transfer (demand mode) request transmission is similar to block transfer, and it is also a way of continuously transmitting data. The difference is: 8237A in the request transmission mode, every byte transmitted will check whether the DREQ signal is valid, if it is valid, then continue to transfer the next byte; if not, stop data transmission and end the DMA process. However, all the transmission sites of the DMA are maintained (the values of the current address register and the current byte counter). When the request signal DREQ is valid again, 8237A continues the data transmission with the original count value and address until the current byte counter is reduced to zero or when the signal is generated by the peripheral, the DMA transmission is terminated and the bus control is released. The characteristic of request transmission mode is that DMA operation can be controlled by peripherals using DREQ signals to control the process of data transmission. (4) Multi-chip cascade (cascade mode) when one piece of 8237A channel is insufficient, the DMA channel can be increased by multi-chip cascade, which is composed of master and slave stages. The HRQ and HLDA pins of slave 8237A are connected with the DREQ and DACK pins of master 8237A, and a master can connect at most four slaves. In the cascade mode, the slave chip is transmitted by DMA, the master chip transmits the contact signal between the slave chip and the CPU, and the priority of each channel of the slave chip is managed. The characteristic of cascading mode is that it can expand multiple DMA channels. After reading the above, do you have any further understanding of the four transmission modes of 8237dma? If you want to know more knowledge or related content, please follow the industry information channel, thank you for your support.

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