Shulou(Shulou.com)06/01 Report--

In this issue, the editor will bring you about the basic principles of SRAM. The article is rich in content and analyzes and narrates it from a professional point of view. I hope you can get something after reading this article.

There is no refresh problem with SRAM. A SRAM basic memory cell is composed of a transistor and two resistors. It does not use capacitors to store data, but by switching the states of transistors. Just as transistors in CPU can represent 0 and these two states respectively by switching different states, it is precisely because of this structure that the reading process of SRAM does not cause the loss of information stored in SRAM. Of course, there is no refresh problem.

Pin definition of SRAM chip

Early SRAM chips used 20-wire dual in-line (DIP) packaging technology, and they had so many pins because they had to:

Each address signal needs a signal line.

A data input line and a data output line

Partial control line (Write Enable, Chip select)

Ground wire and power cord

The following is a schematic diagram of the pin function of a 16Kx1-bitSRAM chip:

AO-A13 is the address input signal pin

/ cS is a chip selection pin, in a practical system, there must be many) RAM chips, so you need to choose which SRAM chip to write or read data from.

/ WE is a write-enabled pin. When SRAM gets an address, it needs to know what to do, whether to write or read. / WE is to call SRAM to write data.

Vcc is the power supply pin

Din is the data entry pin

Dout is the data output pin

GND is a ground pin

This pin is also found in some SRAM chips of Output Enable (/ OE), but not in the figure above. This pin is relative to the function of the / WE: pin, which is to let the lSRAM know that the read operation is performed instead of the write operation.

Overview of read and write operations of SRAM

Reading lbit data from the Dout pin requires the following steps:

SRAM read operation

1) pass the address of the bit to be read through the address bus to the corresponding read address pin (at this time / WE: the pin should not be activated, so SRAM knows that it should not perform write operations)

2) activate / cS select the sram chip

3) activate / OE pin SRAM knows it is a read operation

After the third step, the data to be read is transferred from the DOut pin to the data bus. How can the process be very simple?

Similarly, the process of writing 1bit data is very simple.

SRAM write operation

1) determine the location of the information to be written through the address bus (make sure / OE pin is not activated)

2) transfer the data to be written to the Dout pin through the data bus

3) activate / CS pin select SRAM chip

4) activate / WE pin to inform SRAM that you need to write attentively

After the four steps above, the data that needs to be written is already where it needs to be written.

These are the basic principles of SRAM shared by the editor. If you happen to have similar doubts, you might as well refer to the above analysis to understand. If you want to know more about it, you are welcome to follow the industry information channel.

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